SL11R Cypress Semiconductor Corp, SL11R Datasheet - Page 42

• Manufacturer Part Number: SL11R
• Description: IC MCU FULL SPD USB 16B 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of SL11R

• Applications: USB Microcontroller
• Core Processor: RISC
• Program Memory Type: Mask ROM (6 kB)
• Controller Series: USB Controller
• Ram Size: 3Kx8
• Interface: 2-Wire Serial, UART, USB
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 65°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1462

5.2.4
The external processor can read the STATUS of the OUTBUFF and INBUFF Status bits from this output buffer. The external
ADDR pin should be driven to low when reading this STATUS register.
Note:
The SL11R also can access this register.
5.2.5
The physical interface for the DMA is shared with the Mailbox protocol on the SD15-SD0 bus. If the DREQ (DMA Request Enable)
bit is set, this enables SL11R DMA cycles to or from the external device (scanner, printer, camera, modem or etc.). The DREQ
is asserted by the SL11R when data is ready to be sent or received. When the external device is ready to send Data, it asserts
the nWRITE signal. Data must be available at this point. If the external device is ready to accept data, it asserts the nREAD signal.
The DMA mode can be used to move large amounts of data to or from a variety of peripherals such as Scanners, Printers, Cable
Modems, External Storage devices, and others. For example for a DVC, video data from the camera can be moved via DMA to
an internal memory buffer for subsequent transfer to the USB host. This data can be transferred to the host via the USB DMA
engine (i.e. no SL11R Processing is involved, since the USB has its own DMA engine).
Users can program 8 bit or 16 bit DMA transfers in either direction; Peripheral to SL11R or SL11R to Peripheral. A control register
(0xC02A) sets the DMA bus width, direction and DMA enable and four further registers control the DMA start and end addresses
(see Fast DMA Mode, section 2.14). Furthermore, if the FDMA bit in Register 0xC00E is enabled, an interrupt will be issued to
indicate the DMA operation is complete.
5.2.6
Before setting this register, the Low DMA Start Address (0xC02C), High DMA Start Address (0xC02E), the Low DMA Stop
Address (0xC030) and the High DMA Stop Address (0xC032) must be configured.
5.3
This interface is designed to interface with a specially optimized high-speed EPP interface. The SL11R processor has direct
access to the EPP control port.
The EPP function has four transfer modes: Data Write, Data Read, Address Write and Address Read. Strobe signals nDTSRB
and nASTRB are generated by the SL11R for data or address operations respectively. The signal nWRITE indicates read or write
as described below.
Note:
Document #: 38-08006 Rev. **
• The Fast DMA and PWM Interface will not be supported in this mode.
• Any other unused IO pins can be used as the GPIO pins under control of theGeneral Purpose IO mode (GPIO).
D1
D0
D2
D1
D0
STATUS Register (0xC0C2: Read Only)
DMA Protocol
DMA Control Register (0xC0C0: R/W)
Fast EPP Mode
D15
0
D15
0
D14
0
D14
0
IF
OF
DREQ
D1
D0
D13
0
D13
0
D12
0
D12
0
D11
INBUFF Full
OUTBUFF Full
External DREQ DMA Enable, if set to ‘1’, the SL11R can DMA to or from the external
device (scanner or printer) by asserting the DREQ signal when data is requested or
ready to send.
Set to ‘1’
Set to ‘1’
0
D11
0
D10
0
D10
0
D9
0
D9
0
D8
0
D8
0
D7
0
D7
0
D6
0
D6
0
D5
0
D5
0
D4
0
D4
0
D3
0
D3
0
DREQ
D2
D2
0
D1
IF
D1
D1
OF
D0
D0
D0
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SL11R