SL11R Cypress Semiconductor Corp, SL11R Datasheet - Page 60

• Manufacturer Part Number: SL11R
• Description: IC MCU FULL SPD USB 16B 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of SL11R

• Applications: USB Microcontroller
• Core Processor: RISC
• Program Memory Type: Mask ROM (6 kB)
• Controller Series: USB Controller
• Ram Size: 3Kx8
• Interface: 2-Wire Serial, UART, USB
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 65°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1462

is then used as the byte/word bit, set to “0” to select word or “1” to select byte addressing. In this example, a byte-wide operand
is selected at the memory location pointed to by register R10:
Note:
For register R15, byte-wide operands are prohibited. If bit 3 is set high, the instruction is decoded differently, as explained at the
top of this section.
7.14
Indirect Addressing with Auto Increment works identically to Indirect Addressing, except that at the end of the read or write cycle,
the register is incremented by 1 or 2 (depending whether it is a byte-wide or word-wide access.)
This mode is prohibited for register R15. If bits 0..2 are all high, the instruction is decoded differently, as explained at the top of
this section.
7.15
In Indirect Addressing with Offset, the instruction word is followed by a 16-bit word that is added to the contents of the address
register to form the address for the operand. The offset is an unsigned 16-bit word, and will “wrap” to low memory addresses if
the register and offset add up to a value greater than the size of the processor’s address space.
7.16
Register R15 is designated as the Stack Pointer, and has these special behaviors:
SL11R - CPU Instruction Set
The instruction set can be roughly divided into three classes of instructions:
7.17
Instructions with source and destination, for ALL dual operand instructions, byte values are zero extended by default.
destination:= source
Flags Affected: none
destination:= destination + source
Flags Affected: Z, C, O, S
Document #: 38-08006 Rev. **
Memory operand
MOV
bit:
ADD
bit:
• If addressed in indirect mode, the register pre-decrements on a write instruction, and post-increments on a read instruction,
• Byte-wide reads or writes are prohibited in indirect mode.
• If R15 is addressed in Indirect with Index mode, it does not auto-increment or auto-decrement.
• Dual Operand Instructions (Instructions with two operands, a source and a destination)
• Program Control Instructions (Jump, Call and Return)
• Single Operand Instructions (Instructions with only one operand: a destination)
emulating Push and Pop instructions.
Indirect Addressing with Auto Increment
Indirect Addressing with Offset
Stack Pointer (R15) Special Handling
Dual Operand Instructions
15
15
Bits
14
14
0000
0001
13
13
12
12
5
0
11
11
4
1
10
10
3
1
9
9
source
source
2
0
8
8
1
1
7
7
0
0
6
6
5
5
4
4
Destination
Destination
3
3
2
2
1
1
0
0
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SL11R