MC68340AG25E Freescale Semiconductor, MC68340AG25E Datasheet - Page 119

• Manufacturer Part Number: MC68340AG25E
• Description: IC MPU 32BIT 25MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68340AG25E

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• No. Of I/o's: 16
• Cpu Speed: 25MHz
• No. Of Timers: 2
• Embedded Interface Type: UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Maximum Clock Frequency: 25 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

FRZ0—Freeze Bus Monitor Enable
FIRQ—Full Interrupt Request Mode
SHEN1, SHEN0—Show Cycle Enable
SUPV—Supervisor/User Data Space
IARB3–IARB0—Interrupt Arbitration Bits 3–0
4-22
See Table 4-5 for pin function selection.
These two control bits determine what the EBI does with the external bus during internal
transfer operations (see Table 4-6). A show cycle allows internal transfers to be
externally monitored. The address, data, and control signals (except for AS) are driven
externally. DS is used to signal address strobe timing for show cycles. Data is valid on
the next falling clock edge after DS is negated. However, data is not driven externally,
and AS and DS are not asserted externally for internal accesses unless show cycles
are enabled.
If external bus arbitration is disabled, the EBI will not recognize an external bus request
until arbitration is enabled again. To prevent bus conflicts, external peripherals must not
attempt to initiate cycles during show cycles with arbitration disabled.
The SUPV bit defines the SIM40 registers as either supervisor data space or user
(unrestricted) data space.
These bits are used to arbitrate for the bus in the case that two or more modules
simultaneously generate an interrupt at the same priority level. No two modules can
share the same IARB value. The reset value of IARB is $F, allowing the SIM40 to
arbitrate during an IACK cycle immediately after reset. The system software should
initialize the IARB field to a value from $F (highest priority) to $1 (lowest priority). A
1 = When FREEZE is asserted, the bus monitor is disabled.
0 = When FREEZE is asserted, the bus monitor continues to operate as
1 = Configures port B for seven interrupt request lines, autovector, and no external
0 = Configures port B for four interrupt request lines and four external chip selects.
1 = The SIM40 registers defined as supervisor/user are restricted to supervisor data
0 = The SIM40 registers defined as supervisor/user data are unrestricted (FC2 is a
programmed.
chip selects.
access (FC3–FC0 = $5). An attempted user-space write is ignored and returns
BERR .
don't care).
SHEN1
0
0
1
Freescale Semiconductor, Inc.
SHEN0
For More Information On This Product,
0
1
X
Table 4-6. SHENx Control Bits
MC68340 USER’S MANUAL
Show cycles disabled, external arbitration enabled
Show cycles enabled, external arbitration disabled
Show cycles enabled, external arbitration enabled
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