MC68340AG25E Freescale Semiconductor, MC68340AG25E Datasheet - Page 369

• Manufacturer Part Number: MC68340AG25E
• Description: IC MPU 32BIT 25MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68340AG25E

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• No. Of I/o's: 16
• Cpu Speed: 25MHz
• No. Of Timers: 2
• Embedded Interface Type: UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Maximum Clock Frequency: 25 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

RESET:
PO7–PO0—Prescaler Output
8.4.5 Counter Register (CNTR)
The CNTR reflects the value of the counter. This value can be reliably read at any time
since it is updated on every rising edge of the system clock (except in the input
capture/output compare mode) when a read of the register is not in progress. This read-
only register can be read when the timer module is enabled (i.e. the STP bit in the MCR is
cleared).
CNTR
All 24 bits of the prescaler and the counter may be obtained by one long-word read at the
address of the SR, since the CNTR is contiguous to it. Any changes in the prescaler value
due to the two cycles necessary to perform a long-word read should be considered. If this
latency presents a problem, the TGATE signal may be used to disable the decrement
function while the reads are occurring.
8.4.6 Preload 1 Register (PREL1)
The PREL1 stores a value that is loaded into the counter in some modes of operation.
This value is loaded into the counter on the first falling edge of the counter clock after the
counter is enabled. This register can be be read and written when the timer module is
enabled (i.e. the STP bit in the MCR is cleared). However, a write to this register must be
completed before timeout for the new value to be reliably loaded into the counter.
MOTOROLA
CNT15
15
0
This bit can be used to indicate when a write to the PREL1 or PREL2 registers will not
cause a problem during a counter reload at timeout. To ensure that the write to the
PREL register is recognized at timeout, the latency between the read of the COM bit
and the write to the PREL register must be considered.
These bits show the levels on each of the eight output taps of the prescaler. These
values are updated every time that the system clock goes high and a read cycle of this
byte in the SR is not in progress.
1 = This bit is set when the counter output equals the value in the COM.
0 = This bit is cleared when a timeout occurs, the COM register is accessed (read or
CNT14
14
0
write), the timer is reset with the SWR bit, or the RESET signal is asserted on the
IMB. This bit is cleared regardless of the state of the TC bit.
CNT13
13
0
CNT12
12
0
CNT11
Freescale Semiconductor, Inc.
11
0
For More Information On This Product,
CNT10
10
0
MC68340 USER’S MANUAL
Go to: www.freescale.com
CNT9
9
0
CNT8
8
0
CNT7
7
0
CNT6
6
0
CNT5
5
0
CNT4
4
0
CNT3
3
0
CNT2
Supervisor/User
2
0
$60A, $64A
CNT1
1
0
CNT0
0
0
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