MC68340AG25E Freescale Semiconductor, MC68340AG25E Datasheet - Page 231

• Manufacturer Part Number: MC68340AG25E
• Description: IC MPU 32BIT 25MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68340AG25E

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• No. Of I/o's: 16
• Cpu Speed: 25MHz
• No. Of Timers: 2
• Embedded Interface Type: UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Maximum Clock Frequency: 25 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

Because of the stipulation that each instruction must prefetch to replace itself, the concept
of negative tails has been introduced to account for these free clocks on the bus.
On a two-clock bus, it is not necessary to adjust instruction timing to account for the
potential extra prefetch. The cycle times of the microsequencer and bus are matched, and
no additional benefit or penalty is obtained. In the instruction execution time equations, a
zero should be used instead of a negative number.
Negative tails are used to adjust for slower fetches on slower buses. Normally, increasing
the length of prefetch bus cycles directly affects the cycle count and tail values found in
the tables.
In the following equations, negative tail values are used to negate the effects of a slower
bus. The equations are generalized, however, so that they may be used on any speed bus
with any tail value.
where:
Note that many instructions listed as having negative tails are change-of-flow instructions
and that the bus speed used in the calculation is that of the new instruction stream.
5.7.2 Instruction Stream Timing Examples
The following programming examples provide a detailed examination of timing effects. In
all examples, the memory access is from external synchronous memory, the bus is idle,
and the instruction pipeline is full at the start.
5.7.2.1 TIMING EXAMPLE 1—EXECUTION OVERLAP. Figure 5-33 illustrates execution
overlap caused by the bus controller's completion of bus cycles while the sequencer is
calculating the next EA. One clock is saved between instructions since that is the
minimum time of the individual head and tail numbers.
Instructions
5-94
NEW_TAIL
IF ((NEW_CLOCK – 4) >0) THEN
ELSE
NEW_TAIL/NEW_CYCLE
OLD_TAIL/OLD_CYCLE
NEW_CLOCK
NEW_CYCLE = OLD_CYCLE
NEW_CYCLE = OLD_CYCLE
OLD_TAIL
is the number of clocks per cycle at the slower speed
is the value listed in the instruction timing tables
is the adjusted tail/cycle at the slower speed
(NEW_CLOCK – 2)
Freescale Semiconductor, Inc.
For More Information On This Product,
(NEW_CLOCK -2)
(NEW _CLOCK – 2)
MOVE.W
ADDQ.W
CLR.W
MC68340 USER’S MANUAL
Go to: www.freescale.com
(NEW_CLOCK – 4)
#1, (A0)
A1, (A0)
$30 (A1)
MOTOROLA