MC68340AG25E Freescale Semiconductor, MC68340AG25E Datasheet - Page 284

• Manufacturer Part Number: MC68340AG25E
• Description: IC MPU 32BIT 25MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68340AG25E

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• No. Of I/o's: 16
• Cpu Speed: 25MHz
• No. Of Timers: 2
• Embedded Interface Type: UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Maximum Clock Frequency: 25 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

DAR1, DAR2
U = Unaffected by reset
During the DMA write cycle, this register drives the address on the address bus. This
register can be programmed to increment (CCR DAPI bit set) or remain constant (CCR
DAPI bit cleared) after each operand transfer.
The register is incremented using unsigned arithmetic and will roll over if overflow occurs.
For example, if a register contains $FFFFFFFF and is incremented by 1, it will roll over to
$00000000. This register can be incremented by 1, 2, or 4, depending on the size of the
operand and the starting address. If the operand size is byte, the register is always
incremented by 1. If the operand size is word and the starting address is even-word
aligned, the register is incremented by 2. If the operand size is long word and the address
is even-word aligned, the register is incremented by 4. The DAR value must be aligned to
an even-word boundary if the transfer size is word or long word; otherwise, the CSR
CONF bit is set, and the transfer does not occur.
When read, this register always contains the next destination address. If a bus error
terminates the transfer, this register contains the next destination address that would have
been run had the error not occurred.
6.7.8 Byte Transfer Counter Register (BTC)
The BTC is a 32-bit register that contains the number of bytes left to transfer in a given
block. This register is accessible in either supervisor or user space. The BTC can always
be read or written to when the DMA module is enabled (i.e., the STP bit in the MCR is
cleared).
BTC1, BTC2
U = Unaffected by reset
6-34
RESET:
RESET:
RESET:
RESET:
A31
A15
A31
A15
31
15
31
15
U
U
U
U
A30
A14
A30
A14
30
14
30
14
U
U
U
U
A29
A13
A29
A13
29
13
29
13
U
U
U
U
A28
A12
A28
A12
28
12
28
12
U
U
U
U
A27
A11
A27
A11
27
11
27
11
Freescale Semiconductor, Inc.
U
U
U
U
For More Information On This Product,
A26
A10
A26
A10
26
10
26
10
U
U
U
U
MC68340 USER’S MANUAL
Go to: www.freescale.com
A25
A25
25
A9
25
A9
U
9
U
U
9
U
A24
A24
24
A8
24
A8
U
8
U
U
8
U
A23
A23
23
A7
23
A7
U
7
U
U
7
U
A22
A22
22
A6
22
A6
U
6
U
U
6
U
A21
A21
21
A5
21
A5
U
5
U
U
5
U
A20
A20
20
A4
20
A4
U
4
U
U
4
U
A19
A19
19
A3
19
A3
U
3
U
U
3
U
Supervisor/User
Supervisor/User
A18
A18
18
A2
18
A2
U
2
U
U
2
U
$790, $7B0
$794, $7B4
MOTOROLA
A17
A17
17
A1
17
A1
U
1
U
U
1
U
A16
A16
16
A0
16
A0
U
0
U
U
0
U