MC68340AG25E Freescale Semiconductor, MC68340AG25E Datasheet - Page 274

• Manufacturer Part Number: MC68340AG25E
• Description: IC MPU 32BIT 25MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68340AG25E

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• No. Of I/o's: 16
• Cpu Speed: 25MHz
• No. Of Timers: 2
• Embedded Interface Type: UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Maximum Clock Frequency: 25 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

MCR1, MCR2
STP—Stop Bit
FRZ1, FRZ0—Freeze
6-24
RESET:
STP
15
0
These bits determine the action taken when the FREEZE signal is asserted on the IMB
when the CPU32 has entered background debug mode. The DMA module negates BR
and keeps it negated until FREEZE is negated or reset. Table 6-1 lists the action taken
for each bit combination.
1 = Setting the STP bit stops all clocks within the DMA module except for the clock
0 = The channel operates in normal mode.
FRZ1
14
0
from the IMB. The clock from the IMB remains active to allow the CPU32 access
to the MCR. The clock stops on the low phase of the clock and remains stopped
until the STP bit is cleared by the CPU32 or a hardware reset. Accesses to DMA
module registers while in stop mode produce a bus error. The DMA module
should be disabled in a known state before setting the STP bit. The STP bit
should be set prior to executing the LPSTOP instruction to reduce overall power
consumption.
FRZ0
13
0
The DMA module uses only one STP bit for both channels. A
read or write to either MCR accesses the same STP control bit.
The DMA module uses only one set of FRZx bits for both
channels. A read or write to either MCR accesses the same
FRZx control bits.
12
SE
0
11
Freescale Semiconductor, Inc.
0
0
For More Information On This Product,
*The boundary is defined as any bus cycle by
the DMA module.
FRZ1
Table 6-1. FRZx Control Bits
10
0
0
0
1
1
MC68340 USER’S MANUAL
Go to: www.freescale.com
ISM
9
0
FRZ0
0
1
0
1
8
0
NOTE
NOTE
Freeze on Boundary*
Ignore FREEZE
SUPV
7
1
Reserved
Reserved
Action
6
0
MAID
5
0
4
0
3
0
Supervisor Only
2
0
IARB
$780, $7A0
MOTOROLA
1
0
0
0