MC68340AG25E Freescale Semiconductor, MC68340AG25E Datasheet - Page 208

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MC68340AG25E

Manufacturer Part Number
MC68340AG25E
Description
IC MPU 32BIT 25MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC68340AG25E

Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
144-LQFP
Controller Family/series
68K
Core Size
32 Bit
No. Of I/o's
16
Cpu Speed
25MHz
No. Of Timers
2
Embedded Interface Type
UART
Digital Ic Case Style
LQFP
Rohs Compliant
Yes
Processor Series
M683xx
Core
CPU32
Maximum Clock Frequency
25 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68340AG25E
Manufacturer:
Freescale Semiconductor
Quantity:
135
Part Number:
MC68340AG25E
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
A user can use the state change on DSO to signal hardware that the next serial transfer
may begin. A timeout of sufficient length to trap error conditions that do not change the
state of DSO should also be incorporated into the design. Hardware interlocks in the CPU
prevent result data from corrupting serial transfers in progress.
5.6.2.7.2 Development System Serial Logic. The development system, as the master of
the serial data link, must supply the serial clock. However, normal and BDM operations
could interact if the clock generator is not properly designed.
Breakpoint requests are made by asserting BKPT to the low state in either of two ways.
The primary method is to assert BKPT during a single bus cycle for which an exception is
desired. Another method is to assert BKPT , then continue to assert it until the CPU32
responds by asserting FREEZE. This method is useful for forcing a transition into BDM
when the bus is not being monitored. Each method requires a slightly different serial logic
design to avoid spurious serial clocks.
Figure 5-24 represents the timing required for asserting BKPT during a single bus cycle.
MOTOROLA
SYNCHRONIZED
SYNCHRONIZED
INTERNAL
INTERNAL
CLKOUT
WINDOW
CLKOUT
FREEZE
SAMPLE
DSCLK
DSCLK
DSO
.
DSI
DSI
Figure 5-23. Serial Interface Timing Diagram
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68340 USER’S MANUAL
Go to: www.freescale.com
5- 71

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