MC68340AG25E Freescale Semiconductor, MC68340AG25E Datasheet - Page 327

• Manufacturer Part Number: MC68340AG25E
• Description: IC MPU 32BIT 25MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68340AG25E

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• No. Of I/o's: 16
• Cpu Speed: 25MHz
• No. Of Timers: 2
• Embedded Interface Type: UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Maximum Clock Frequency: 25 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

7.4.1.11 AUXILIARY CONTROL REGISTER (ACR). The ACR selects which baud rate is
used and controls the handshake of the transmitter/receiver. This register can only be
written when the serial module is enabled (i.e., the STP bit in the MCR is cleared).
BRG—Baud Rate Generator Set Select
IECB, IECA—Input Enable Control
7.4.1.12 INTERRUPT STATUS REGISTER (ISR). The ISR provides status for all potential
interrupt sources. The contents of this register are masked by the IER. If a flag in the ISR
is set and the corresponding bit in IER is also set, the IRQ output is asserted. If the
corresponding bit in the IER is cleared, the state of the bit in the ISR has no effect on the
output. This register can only be read when the serial module is enabled (i.e., the STP bit
in the MCR is cleared).
COS—Change-of-State
7-32
1 = Set 2 of the available baud rates is selected.
0 = Set 1 of the available baud rates is selected. Refer to 7.4.1.6 Clock-Select
1 = ISR bit 7 will be set and an interrupt will be generated when the corresponding bit
0 = Setting the corresponding bit in the IPCR has no effect on ISR bit 7.
1 = A change-of-state has occurred at one of the CTS inputs and has been
0 = The CPU32 has read the IPCR.
Register (CSR) for more information on the baud rates.
in the IPCR (COSB or COSA) is set by an external transition on the channel's
CTS input (if bit 7 of the interrupt enable register (IER) is set to enable
interrupts).
selected to cause an interrupt by programming bit 1 and/or bit 0 of the ACR.
The IER does not mask reading of the ISR. True status is
provided regardless of the contents of IER. The contents of
ISR are cleared when the serial module is reset.
ACR
Write Only
ISR
Read Only
RESET:
RESET:
BRG
COS
Freescale Semiconductor, Inc.
7
0
7
0
For More Information On This Product,
DBB
6
0
0
6
0
MC68340 USER’S MANUAL
RxRDYB TxRDYB XTAL_
Go to: www.freescale.com
5
0
0
5
0
4
0
0
4
0
NOTE
RDY
3
0
0
3
1
Supervisor/User
Supervisor/User
DBA
2
0
0
2
0
RxRDYA TxRDYA
IECB
1
0
1
0
$714
$715
IECA
0
0
0
0
MOTOROLA