MC68340AG25E Freescale Semiconductor, MC68340AG25E Datasheet - Page 319

• Manufacturer Part Number: MC68340AG25E
• Description: IC MPU 32BIT 25MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68340AG25E

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• No. Of I/o's: 16
• Cpu Speed: 25MHz
• No. Of Timers: 2
• Embedded Interface Type: UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Maximum Clock Frequency: 25 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

7.4.1.5 STATUS REGISTER (SR). The SR indicates the status of the characters in the
FIFO and the status of the channel transmitter and receiver. This register can only be read
when the serial module is enabled (i.e., the STP bit in the MCR is cleared).
RB—Received Break
FE—Framing Error
PE—Parity Error
7-24
1 = An all-zero character of the programmed length has been received without a stop
0 = No break has been received.
1 = A stop bit was not detected when the corresponding data character in the FIFO
0 = No framing error has occurred.
1 = When the with parity or force parity mode is programmed in the MR1, the
0 = No parity error has occurred.
bit. The RB bit is only valid when the RxRDY bit is set. Only a single FIFO
position is occupied when a break is received. Further entries to the FIFO are
inhibited until the channel RxDx returns to the high state for at least one-half bit
time, which is equal to two successive edges of the internal or external 1 clock
or 16 successive edges of the external 16 clock.
The received break circuit detects breaks that originate in the middle of a
received character. However, if a break begins in the middle of a character, it
must persist until the end of the next detected character time.
was received. The stop-bit check is made in the middle of the first stop-bit
position. The bit is valid only when the RxRDY bit is set.
corresponding character in the FIFO was received with incorrect parity. When the
multidrop mode is programmed, this bit stores the received A/D bit. This bit is
valid only when the RxRDY bit is set.
SRA, SRB
Read Only
RESET:
RB
Freescale Semiconductor, Inc.
7
0
For More Information On This Product,
B/C1
Table 7-3. B/Cx Control Bits
FE
6
0
0
0
1
1
MC68340 USER’S MANUAL
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PE
5
0
B/C0
0
1
0
1
OE
4
0
TxEMP
Bits/Character
3
0
Seven Bits
Eight Bits
Five Bits
Six Bits
TxRDY
Supervisor/User
2
0
$711, $719
FFULL
1
0
RxRDY
0
0
MOTOROLA