MC68340AG25E Freescale Semiconductor, MC68340AG25E Datasheet - Page 329

• Manufacturer Part Number: MC68340AG25E
• Description: IC MPU 32BIT 25MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68340AG25E

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• No. Of I/o's: 16
• Cpu Speed: 25MHz
• No. Of Timers: 2
• Embedded Interface Type: UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Maximum Clock Frequency: 25 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

RxRDYA—Channel A Receiver Ready or FIFO Full
TxRDYA—Channel A Transmitter Ready
7.4.1.13 INTERRUPT ENABLE REGISTER (IER). The IER selects the corresponding bits
in the ISR that cause an interrupt output ( IRQ ). If one of the bits in the ISR is set and the
corresponding bit in the IER is also set, the IRQ output is asserted. If the corresponding
bit in the IER is zero, the state of the bit in the ISR has no effect on the IRQ output. The
IER does not mask the reading of the ISR. The ISR XTAL_RDY bit cannot be enabled to
generate an interrupt. This register can only be written when the serial module is enabled
(i.e., the STP bit in the MCR is cleared).
COS—Change-of-State
DBB—Delta Break B
7-34
The function of this bit is programmed by MR1A bit 6.
This bit is the duplication of the TxRDY bit in SRA.
1 = If programmed as receiver ready, a character has been received in channel A
0 = If programmed as receiver ready, the CPU32 has read the receiver buffer. After
1 = The transmitter holding register is empty and ready to be loaded with a character.
0 = The transmitter holding register was loaded by the CPU32, or the transmitter is
1 = Enable interrupt
0 = Disable interrupt
1 = Enable interrupt
0 = Disable interrupt
and is waiting in the receiver buffer FIFO. If programmed as FIFO full, a
character has been transferred from the receiver shift register to the FIFO, and
the transfer has caused the channel A FIFO to become full (all three positions
are occupied).
this read, if more characters are still in the FIFO, the bit is set again after the
FIFO is 'popped'. If programmed as FIFO full, the CPU32 has read the receiver
buffer. If a character is waiting in the receiver shift register because the FIFO is
full, the bit will be set again when the waiting character is loaded into the FIFO.
This bit is set when the character is transferred to the transmitter shift register.
This bit is also set when the transmitter is first enabled. Characters loaded into
the transmitter holding register while the transmitter is disabled are not
transmitted.
disabled.
IER
Write Only
RESET:
COS
Freescale Semiconductor, Inc.
7
0
For More Information On This Product,
DBB
6
0
MC68340 USER’S MANUAL
RxRDYB TxRDYB
Go to: www.freescale.com
5
0
4
0
3
0
0
Supervisor/User
DBA
2
0
RxRDYA TxRDYA
1
0
$715
0
0
MOTOROLA