MC68340AG25E Freescale Semiconductor, MC68340AG25E Datasheet - Page 130

• Manufacturer Part Number: MC68340AG25E
• Description: IC MPU 32BIT 25MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68340AG25E

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• No. Of I/o's: 16
• Cpu Speed: 25MHz
• No. Of Timers: 2
• Embedded Interface Type: UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Maximum Clock Frequency: 25 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

4.3.4.3 CHIP SELECT REGISTERS PROGRAMMING EXAMPLE. The following listing is
an example of programming a chip select at starting address $00040000, for a block size
of 256 Kbytes, accessing supervisor and user data spaces with a 16-bit port requiring two
wait states. There will be no write protection, no fast termination, and no CPU space
accesses.
4.3.5 External Bus Interface Control
The following paragraphs describe the registers that control the I/O pins used with the
EBI. Refer to the Section 3 Bus Operation for more information about the EBI. For a list
of pin numbers used with port A and port B, see the pinout diagram in Section 12
Ordering Information and Mechanical Data. Section 2 Signal Descriptions shows a
block diagram of the port control circuits.
4.3.5.1 PORT A PIN ASSIGNMENT REGISTER 1 (PPARA1). PPARA1 selects between
an address and discrete I/O function for the port A pins. Any set bit defines the
corresponding pin to be an I/O pin, controlled by the port A data and data direction
registers. Any cleared bit defines the corresponding pin to be an address bit as defined in
the following register diagram. Bits set in this register override the configuration setting of
PPARA2. The $FF reset value of PPARA1 configures it as an input port. This register can
be read or written at any time.
MOTOROLA
If an access matches multiple chip selects, the lowest
numbered chip select will have priority. For example, if CS0
and CS2 "overlap" for a certain range, CS0 will assert when
accessing the "overlapped" address range, and CS2 will not.
PPARA1
RESET:
PRTA7
Freescale Semiconductor, Inc.
(A31)
1
7
For More Information On This Product,
PRTA6
(A30)
1
6
address mask 1 = $0003
address mask 2 = $FF49
base address 1 = $0004
base address 2 = $0013
MC68340 USER’S MANUAL
Go to: www.freescale.com
PRTA5
(A29)
1
5
PRTA4
(A28)
1
NOTE
4
PRTA3
(A27)
1
3
PRTA2
Supervisor Only
(A26)
1
2
PRTA1
(A25)
1
1
$015
PRTA0
(A24)
1
0
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