W83627DHG Nuvoton Technology Corporation of America, W83627DHG Datasheet - Page 120

• Manufacturer Part Number: W83627DHG
• Description: IC I/O CONTROLLER 128-QFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627DHG

• Applications: PC's, PDA's
• Interface: LPC
• Voltage - Supply: 3.3V
• Package / Case: 128-XFQFN
• Mounting Type: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.
The W83627DHG provides a bridge of the Low Pin Count (LPC) Interface to Serial Peripheral Interface
(SPI). The signals in the SPI are transmitted through Pin 2 (SCK), Pin 19 (SCE#), Pin 58 (SI), and Pin
118 (SO). In the Super I/O (W83627DHG), these 4 pins are multi-functional. The SPI functions are
activated through strapping. Pin 52 determines whether to enable or disable the SPI functions. In the
Super I/O (W83627DHG), the SPI functions are activated when Pin 52 is pulled-up to the power source.
The function status can be seen/read at CR[24h], bit 1.
The SPI is primarily used to store the BIOS ROM. When booting the computer, the memory read
instructions or timing sequences are transmitted from the CPU, the South Bridge, the LPC bus to the
Super I/O (W83627DHG). After receiving the instruction, the Super I/O (W83627DHG) generates and
transmits the correct instructions and memory addresses to the SPI which responds with the
corresponding data of the addresses. The data are placed to the LPC bus by the Super I/O
(W83627DHG) and returned to the South Bridge. All of the data are read in this manner. By setting the
registers shown at Table 9.3, the Super I/O (W83627DHG) supports all the instructions given, such as
erase, read, program, to SPI flash. For more details, please see Table 9.2.
To make it more user-friendly, regularly used SPI instructions/functions can be generated via the LPC
I/O read/write commands. That is, the flash devices with SPI can be programmed, erased, or read on
the motherboard.
9.1
LOGICAL DEVICE
SERIAL PERIPHERAL INTERFACE
Using the SPI Interface via the LPC
6
The allowed range is 8 bytes above the base address. The base address is configured at
Configuration Register CR62h and CR63h in Logical Device 6. For example, if 03h is
written to Configuration Register CR62h, and F8h to Configuration Register CR63h, 03F8h
~ 03FFh is the allowed range.
CONFIGURATION
REGISTER
Table 9.1 Base Address Setting
62
63
-108-
BIT
7:0
7:0
Publication Release Date: Aug, 22, 2007
High byte of Base Address
Low byte of Base Address
FUNCTION
W83627DHG
Version 1.4