W83627DHG Nuvoton Technology Corporation of America, W83627DHG Datasheet - Page 152

• Manufacturer Part Number: W83627DHG
• Description: IC I/O CONTROLLER 128-QFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627DHG

• Applications: PC's, PDA's
• Interface: LPC
• Voltage - Supply: 3.3V
• Package / Case: 128-XFQFN
• Mounting Type: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.2.3 Handshake Control Register (HCR) (Read/Write)
This register controls pins used with handshaking peripherals such as modems and also controls the
diagnostic mode of the UART.
Bit 4: When this bit is set to logical 1, the UART enters diagnostic mode, as follows:
DTR (bit 0 of HCR)→DSR#, RTS (bit 1 of HCR) →CTS#, Loopback RI input (bit 2 of HCR) → RI# and
IRQ enable (bit 3 of HCR) →DCD#.
Bit 3: The UART interrupt output is enabled by setting this bit to logical 1. In diagnostic mode, this bit is
Bit 2: This bit is only used in the diagnostic mode. In diagnostic mode, this bit is internally connected to
Bit 1: This bit controls the RTS# output. The value of this bit is inverted and output to RTS#.
Bit 0: This bit controls the DTR# output. The value of this bit is inverted and output to DTR#.
11.2.4 Handshake Status Register (HSR) (Read/Write)
This register reflects the current state of the four input pins used with handshake peripherals such as
modems and records changes on these pins.
Bit 7: This bit is the opposite of the DCD# input. This bit is equivalent to bit 3 of HCR in loopback mode.
Bit 6: This bit is the opposite of the RI # input. This bit is equivalent to bit 2 of HCR in loopback mode.
Bit 5: This bit is the opposite of the DSR# input. This bit is equivalent to bit 0 of HCR in loopback mode.
Bit 4: This bit is the opposite of the CTS# input. This bit is equivalent to bit 1 of HCR in loopback mode.
Aside from the above connections, the UART operates normally. This method allows the CPU to
test the UART in a convenient way.
(1) SOUT is forced to logical 1, and SIN is isolated from the communication link.
(2) The modem output pins are set to their inactive state.
(3) The modem input pins are isolated from the communication link and connect internally as
internally connected to the modem control input DCD#.
the modem control input RI#.
7
0
7
0
6
6
5
0
5
4
4
3
3
2
2
1
1
-140-
0
0
Clear to send (CTS)
Data set ready (DSR)
Ring indicator (RI)
Data carrier detect (DCD)
CTS# toggling (TCTS)
RI falling edge (FERI)
DCD# toggling (TDCD)
DSR# toggling (TDSR)
Data terminal ready (DTR)
Request to send (RTS)
Loopback RI input
IRQ enable
Internal loopback enable
Publication Release Date: Aug, 22, 2007
W83627DHG
Version 1.4