W83627DHG Nuvoton Technology Corporation of America, W83627DHG Datasheet - Page 88

• Manufacturer Part Number: W83627DHG
• Description: IC I/O CONTROLLER 128-QFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627DHG

• Applications: PC's, PDA's
• Interface: LPC
• Voltage - Supply: 3.3V
• Package / Case: 128-XFQFN
• Mounting Type: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bit 7: CASEOPEN Clear Control. Write 1 to this bit will clear CASEOPEN status. This bit won’t be self
Bit 6-3: Reserved.
Bit 2-1: A one disables the corresponding interrupt status bit for the SMI interrupt. (See Interrupt
Bit 0: Reserved.
8.37 Fan Divisor Register I - Index 47h (Bank 0)
Register Location:
Power on Default Value:
Attribute:
Size:
Bit 7-6: CPUFANIN0 Divisor, bits1-0. (See VBAT Monitor Control Register - Index 5Dh (Bank 0))
Bit 5-4: SYSFANIN Divisor, bits1-0. (See VBAT Monitor Control Register - Index 5Dh (Bank 0))
Bit 3: CPUFANIN1 output value, only if bit 2 is set to zero. Otherwise, this bit has no meaning.
Bit 2: CPUFANIN1 Input Control.
Bit 1: AUXFANIN1 output value, only if bit 0 is set to zero. Otherwise, this bit has no meaning.
Bit 0: AUXFANIN1 Input Control.
cleared, please write 0 after event be cleared. The function is the same as LDA, CR[E6h] bit 5.
1: Pin119(CPUFANIN1) generates a logic-high signal.
0: Pin119 generates a logic-low signal. (Default)
1: Pin119 (CPUFANIN1) acts as a FAN tachometer input. (Default)
0: Pin119 acts as a FAN control signal, and the output value is set by register bit 3.
1: Pin58(AUXFANIN1) generates a logic-high signal.
0: Pin58 generates a logic-low signal. (Default)
Status Register 3 - Index 50h (Bank 4))
7
7
55h
47h
8 bits
Read/Write
6
6
5
5
4
4
3
3
2
2
1
-76-
1
0
0
FANINC5
FANOPV5
FANINC4
FANOPV4
SYSFANIN DIV_B0
SYSFANIN DIV_B1
CPUFANIN0 DIV_B0
CPUFANIN0 DIV_B1
Reserved
CPUFANIN1
AUXFANIN1
Reserved
Reserved
Reserved
Reserved
CaseOpen Clear
Publication Release Date: Aug, 22, 2007
W83627DHG
Version 1.4