W83627DHG Nuvoton Technology Corporation of America, W83627DHG Datasheet - Page 168

• Manufacturer Part Number: W83627DHG
• Description: IC I/O CONTROLLER 128-QFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627DHG

• Applications: PC's, PDA's
• Interface: LPC
• Voltage - Supply: 3.3V
• Package / Case: 128-XFQFN
• Mounting Type: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bit 2: Read/Write
Bit 1: Read only
Bit 0: Read only
12.3.11 ECP Pin Descriptions
NStrobe (HostClk)
PD<7:0>
nAck (PeriphClk)
Busy (PeriphAck)
PError (nAckReverse)
Select (Xflag)
NAME
1
0
0
1
0
1
Disables DMA and all of the service interrupts. Writing a logical 1 to this bit does not
cause an interrupt.
Enables one of the following cases of interrupts. When one of the serviced interrupts
occurs, this bit is set to logical 1 by the hardware. This bit must be reset to logical 0
to re-enable the interrupts.
(a) dmaEn = 1: During DMA, this bit is set to logical 1 when terminal count is
reached.
(b) dmaEn = 0, direction = 0: This bit is set to logical 1 whenever there are writeIntr
threshold or more bytes free in the FIFO.
(c) dmaEn = 0, direction = 1: This bit is set to logical 1 whenever there are readIntr
threshold or more valid bytes to be read from the FIFO.
The FIFO has at least one free byte.
The FIFO is completely full; it cannot accept another byte.
The FIFO contains at least one byte of data.
The FIFO is completely empty.
TYPE
I/O
O
I
I
I
I
This pin loads data or address into the slave on its asserting edge
during write operations. This signal handshakes with Busy.
These signals contain address, data or RLE data.
This signal indicates valid data driven by the peripheral when
asserted. This signal handshakes with nAutoFd in reverse.
This signal deasserts to indicate that the peripheral can accept
data. In the reverse direction, it indicates whether the data lines
contain ECP command information or data. Normal data are
transferred when Busy (PeriphAck) is high, and an 8-bit command
is transferred when it is low.
This signal is used to acknowledge a change in the direction of the
transfer (asserted = forward). The peripheral drives this signal low
to
nAckReverse to determine when it is permitted to drive the data
bus.
Indicates printer on-line.
acknowledge
-156-
nReverseRequest.
DESCRIPTION
Publication Release Date: Aug, 22, 2007
The
W83627DHG
host
relies
Version 1.4
upon