W83627DHG Nuvoton Technology Corporation of America, W83627DHG Datasheet - Page 143

• Manufacturer Part Number: W83627DHG
• Description: IC I/O CONTROLLER 128-QFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627DHG

• Applications: PC's, PDA's
• Interface: LPC
• Voltage - Supply: 3.3V
• Package / Case: 128-XFQFN
• Mounting Type: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DRATE1 DRATE0 (Bit 1, 0):
These two bits select the data rate of the FDC and reduced write-current control.
00
01
10
11
The 2 MB/S data rate for the tape drive is only supported by setting DRATE1 and DRATE0 to 01, as
well as setting DRT1 and DRT0 (CRF4 and CRF5 for logical device 0) to 10. Please see the functional
description of CRF4 or CRF5 and the data rate table for individual data-rate settings.
10.2.7 FIFO Register (R/W base address + 5)
The FIFO register consists of four status registers in a stack, and only one register is presented to the
data bus at a time. The FIFO register stores data, commands, and parameters, and it provides
disk-drive status information. In addition, data bytes pass through the data register to program or obtain
results after a command. In the W83627DHG, this register is disabled after reset. The FIFO can enable
it and change its values through the configure command.
Status Register 0 (ST0)
7-6
500 KB/S (MFM), 250 KB/S (FM), RWC# = 1
300 KB/S (MFM), 150 KB/S (FM), RWC# = 0
250 KB/S (MFM), 125 KB/S (FM), RWC# = 0
1 MB/S (MFM), Illegal (FM), RWC# = 1
5
4
3
2
1-0
US1, US0 Drive Select:
00 Drive A selected
01 Reserved
10 Reserved
11 Reserved
HD Head address:
1 Head selected
0 Head selected
NR Not Ready:
1 Drive is not ready
0 Drive is ready
EC Equipment Check:
1 When a fault signal is received from the FDD or the track
0 signal fails to occur after 77 step pulses
0 No error
SE Seek end:
1 seek end
0 seek error
IC Interrupt Code:
00 Normal termination of command
01 Abnormal termination of command
10 Invalid command issue
11 Abnormal termination because the ready signal from FDD changed state during command execution
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Publication Release Date: Aug, 22, 2007
W83627DHG
Version 1.4