W83627DHG Nuvoton Technology Corporation of America, W83627DHG Datasheet - Page 185

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W83627DHG

Manufacturer Part Number
W83627DHG
Description
IC I/O CONTROLLER 128-QFP
Manufacturer
Nuvoton Technology Corporation of America
Datasheet

Specifications of W83627DHG

Applications
PC's, PDA's
Interface
LPC
Voltage - Supply
3.3V
Package / Case
128-XFQFN
Mounting Type
Surface Mount
Pin Count
128
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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0
15. SERIALIZED IRQ
The W83627DHG supports a serialized IRQ scheme. This allows a signal line to be used to report the
parallel interrupt requests. Since more than one device may need to share the signal serial SERIRQ
signal, an open drain signal scheme is employed. The clock source is the PCI clock. The serialized
interrupt is transferred on the SERIRQ signal, one cycle consisting of three frames types: the Start
Frame, the IRQ/Data Frame, and the Stop Frame.
15.1 Start Frame
There are two modes of operation for the SERIRQ Start Frame: Quiet mode and Continuous mode.
In the Quiet mode, the W83627DHG drives the SERIRQ signal active low for one clock, and then
tri-states it. This brings all the state machines of the W83627DHG from idle to active states. The host
controller (the South Bridge) then takes over driving SERIRQ signal low in the next clock and continues
driving the SERIRQ low for programmable 3 to 7 clock periods. This makes the total number of clocks
low 4 to 8 clock periods. After these clocks, the host controller drives the SERIRQ high for one clock
and then tri-states it.
In the Continuous mode, the START Frame can only be initiated by the host controller to update the
information of the IRQ/Data Frame. The host controller drives the SERIRQ signal low for 4 to 8 clock
periods. Upon a reset, the SERIRQ signal is defaulted to the Continuous mode for the host controller to
initiate the first Start Frame.
Please see the diagram below for more details.
H=Host Control
Note:
1. The Start Frame pulse can be 4-8 clocks wide.
2. The first clock of Start Frame is driven low by the W83627DHG because IRQ1 of the W83627DHG
needs an interrupt request. Then the host takes over and continues to pull the SERIRQ low.
PCICLK
SER IRQ
Drive Source
Start Frame Timing with source sampled a low pulse on IRQ1.
IRQ1
SL
or
H
SL=Slave Control
2
START
Host Controller
START FRAME
H
1
R
T
R=Recovery
-173-
IRQ0 FRAME
S
None
R
T
Publication Release Date: Aug, 22, 2007
T=Turn-around
IRQ1 FRAME
S
IRQ1
R
W83627DHG
T
SMI# FRAME
S
None
R
S=Sample
Version 1.4
T

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