W83627DHG Nuvoton Technology Corporation of America, W83627DHG Datasheet - Page 150

• Manufacturer Part Number: W83627DHG
• Description: IC I/O CONTROLLER 128-QFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627DHG

• Applications: PC's, PDA's
• Interface: LPC
• Voltage - Supply: 3.3V
• Package / Case: 128-XFQFN
• Mounting Type: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

BDLAB = 0
BDLAB = 0
BDLAB = 0
BDLAB = 1
BDLAB = 1
*: Bit 0 is the least significant bit. The least significant bit is the first bit serially transmitted or received.
**: These bits are always 0 in 16450 Mode.
+ 0
+ 0
+ 1
+ 0
+ 1
Register Address
+ 2
+ 2
+ 3
+ 4
+ 5
+ 6
+ 7
Base
UART Status
User Defined
Divisor Latch
Divisor Latch
(Read Only)
(Write Only)
(Read Only)
UART FIFO
(Write Only)
Transmitter
Handshake
Handshake
Baudrate
Receiver
Register
Register
Interrupt
Register
Interrupt
Register
Register
Register
Register
Register
Register
Register
Baudrate
Control
Control
Control
Control
Status
Status
Buffer
Buffer
UART
High
Low
UCR
HCR
UDR
RBR
UFR
USR
HSR
TBR
BHL
BLL
ICR
ISR
RX Data
TX Data
RBR Data
RBR Data
Terminal
Toggling
Interrupt
(ERDRI)
Interrupt
Pending
(TCTS)
(DLS0)
Enable
Enable
Length
Ready
Ready
Ready
Select
(DTR)
(RDR)
FIFO
"0" if
Data
Data
Bit 0
Bit 0
Bit 0
CTS
Bit 0
Bit 0
Bit 8
0
RX Data
(ETBREI)
Interrupt
Toggling
TX Data
Interrupt
Request
Overrun
(TDSR)
Enable
Length
(DLS1)
Empty
Status
RCVR
Select
(OER)
Bit (0)
(RTS)
Reset
FIFO
Send
Error
Data
DSR
Bit 1
Bit 1
TBR
Bit 1
Bit 1
Bit 1
Bit 9
to
1
Loopback
RI Falling
Stop Bits
Parity Bit
RX Data
TX Data
(EUSRI)
Interrupt
(MSBE)
Multiple
(PBER)
Interrupt
Enable
Enable
Status
(FERI)
Bit (1)
Reset
Bit 10
XMIT
FIFO
Edge
Input
Error
Bit 2
Bit 2
Bit 2
Bit 2
USR
RI
2
-138-
Bit Number
Toggling
RX Data
Interrupt
(EHSRI)
Interrupt
TX Data
No Stop
Bit (2)**
(NSER)
(TDCD)
Enable
Enable
Enable
Status
Select
(PBE)
Mode
Parity
Bit 11
DMA
Error
HSR
DCD
Bit 3
Bit 3
Bit 3
Bit 3
IRQ
Bit
Bit
3
Publication Release Date: Aug, 22, 2007
Loopback
Reserved Reversed
Detected
RX Data
TX Data
Internal
to Send
Enable
Enable
(EPE)
(SBD)
(CTS)
Parity
Silent
Bit 12
Clear
Even
Bit 4
Bit 4
Byte
Bit 4
Bit 4
4
0
0
RX Data
TX Data
Bit Fixed
Data Set
(TBRE)
Enable
PBFE)
Empty
Ready
(DSR)
Parity
Bit 13
Bit 5
Bit 5
TBR
Bit 5
Bit 5
5
0
0
0
W83627DHG
RX Data
Interrupt
Indicator
TX Data
Enabled
Silence
(TSRE)
Enable
FIFOs
Active
Empty
(SSE)
(LSB)
Bit 14
Level
Ring
Bit 6
Bit 6
TSR
Bit 6
Bit 6
(RI)
Set
RX
**
6
0
0
Version 1.4
Access Bit
RX Data
Indication
Baudrate
(BDLAB)
RX FIFO
(RFEI) **
TX Data
Enabled
Interrupt
Divisor
Carrier
(MSB)
Detect
(DCD)
FIFOs
Active
Bit 15
Level
Latch
Error
Data
Bit 7
Bit 7
Bit 7
Bit 7
RX
**
7
0
0