W83627DHG Nuvoton Technology Corporation of America, W83627DHG Datasheet - Page 146

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W83627DHG

Manufacturer Part Number
W83627DHG
Description
IC I/O CONTROLLER 128-QFP
Manufacturer
Nuvoton Technology Corporation of America
Datasheet

Specifications of W83627DHG

Applications
PC's, PDA's
Interface
LPC
Voltage - Supply
3.3V
Package / Case
128-XFQFN
Mounting Type
Surface Mount
Pin Count
128
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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0
DSKCHG (Bit 7):
This bit indicates the status of the DSKCHG# input.
Bit 6-4: These bits are always a logic 0 during a read.
DMAEN (Bit 3):
This bit indicates the value of DO register, bit 3.
NOPREC (Bit 2):
This bit indicates the value of the NOPREC bit in the CC REGISTER.
DRATE1 DRATE0 (Bit 1, 0):
These two bits select the data rate of the FDC. See DR register bits 1 and 0 (Data Rate Register (DR
Register) (Write base address + 4)) for how the settings correspond to individual data rates.
10.2.9 Configuration Control Register (CC Register) (Write base address + 7)
This register is used to control the data rate. In PC/AT and PS/2 mode, the bit definitions are as follows:
Bit 7-2: Reserved. These bits should be set to 0.
DRATE1 DRATE0 (Bit 1, 0):
These two bits select the data rate of the FDC. See DR register bits 1 and 0 (Data Rate Register (DR
Register) (Write base address + 4)) for how the settings correspond to individual data rates.
x
7
7
x
6
6
0
x
5
5
0
0
x
4
4
X: Reserved
3
x
3
-134-
2
x
2
1
1
0
DSKCHG#
DRATE0
DRATE1
NOPREC
DMAEN
0
Publication Release Date: Aug, 22, 2007
DRATE0
DRATE1
W83627DHG
Version 1.4

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