W83627DHG Nuvoton Technology Corporation of America, W83627DHG Datasheet - Page 183

• Manufacturer Part Number: W83627DHG
• Description: IC I/O CONTROLLER 128-QFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627DHG

• Applications: PC's, PDA's
• Interface: LPC
• Voltage - Supply: 3.3V
• Package / Case: 128-XFQFN
• Mounting Type: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 14.4
Note. 1. The values above are the worst-case results of R&D simulation
Additionally, the ATXPGD signal, too, is used to control the generation of PWROK and PWROK2. In
Figure 14.8, the 3VCC voltage rises to “V3”, and then starts a delay – “t2” for PWROK and PWROK2
generation. However, ATXPGD is still inactive after t2; therefore the delay time before the rising edge
of PWROK and PWROK2 are t2 plus Td. The length of Td is based on when the ATXPGD signal is
active. Once 3VCC falls below “V4” or the ATXPGD signal is inactive, PWROK and PWROK2 de-assert
immediately.
In Figure 14.9, the 3VCC voltage rises to “V3”, and the ATXPGD is active during t2, so PWROK and
PWROK2 assert after t2. The timing of t2 starts when 3VCC voltage rises to “V3”. No matter the
ATXPGD signal activation is during or after t2, PWROK and PWROK2 assert or de-assert according to
the 3VCC voltage and the ATXPGD signal.
PWROK/PWROK2
(output)
ATXPGD(input)
3VCC
SYMBOL
2. The length of T
t3
V3
t2
FTPRST# active to PWROK active
L
Td
level is based on the length of the low level of FTPRST#
PARAMETER
PWROK/PWROK2 are
active when both 3VCC
and ATXPGD are valid
Figure 14.8
-171-
Publication Release Date: Aug, 22, 2007
V4
MIN
28
W83627DHG
MAX
PWROK/PWROK2
are inactive when
either 3VCC or
ATXPGD is invalid
39
Version 1.4
UNIT
mS