W83627DHG Nuvoton Technology Corporation of America, W83627DHG Datasheet - Page 155

• Manufacturer Part Number: W83627DHG
• Description: IC I/O CONTROLLER 128-QFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627DHG

• Applications: PC's, PDA's
• Interface: LPC
• Voltage - Supply: 3.3V
• Package / Case: 128-XFQFN
• Mounting Type: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.2.7 Interrupt Control Register (ICR) (Read/Write)
This 8-bit register enables and disables the five types of controller interrupts separately. A selected
interrupt can be enabled by setting the appropriate bit to logical 1. The interrupt system can be totally
disabled by setting bits 0 through 3 to logical 0.
Bit 7-4: These four bits are always logical 0.
Bit 3: EHSRI. Set this bit to logical 1 to enable the handshake status register interrupt.
Bit 2: EUSRI. Set this bit to logical 1 to enable the UART status register interrupt.
Bit 1: ETBREI. Set this bit to logical 1 to enable the TBR empty interrupt.
Bit 0: ERDRI. Set this bit to logic 1 to enable the RBR data ready interrupt.
11.2.8 Programmable Baud Generator (BLL/BHL) (Read/Write)
Two 8-bit registers, BLL and BHL, compose a programmable baud generator that uses 24 MHz to
generate a 1.8461 MHz frequency and divide it by a divisor from 1 to (2
the baud generator is the baud rate multiplied by 16, and this is the base frequency for the transmitter
and receiver. The table below illustrates the use of the baud generator with a frequency of 1.8461
MHz. In high-speed UART mode (CR0C, bits 7 and 6), the programmable baud generator directly uses
24 MHz and the same divisor as the normal speed divisor. As a result, in high-speed mode, the data
transmission rate can be as high as 1.5M bps.
PRE-DIV: 13
1.8461M HZ
134.5
1200
1800
2000
110
150
300
600
50
75
7
0
PRE-DIV:1.625
14.769M HZ
0
6
14400
16000
1076
1200
2400
4800
9600
400
600
880
5
0
BAUD RATE FROM DIFFERENT PRE-DIVIDER
4
0
3
PRE-DIV: 1.0
24M HZ
2
1478.5
15600
23400
26000
1430
1950
3900
7800
650
975
1
0
RBR data ready interrupt enable (ERDRI)
TBR empty interrupt enable (ETBREI)
UART receive status interrupt enable (EUSRI)
Handshake status interrupt enable (EHSRI)
DECIMAL DIVISOR
-143-
GENERATE 16X
USED TO
CLOCK
2304
1536
1047
857
768
384
192
96
64
58
Publication Release Date: Aug, 22, 2007
16
–1). The output frequency of
ERROR PERCENTAGE
W83627DHG
0.099%
0.18%
0.53%
**
**
**
**
**
**
**
Version 1.4