PI7C9X110BNBE Pericom Semiconductor, PI7C9X110BNBE Datasheet
PI7C9X110BNBE
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PI7C9X110 PCI Express-to-PCI Reversible Bridge Revision 3.0 ST 3545 North 1 Street, San Jose, CA 95134 Phone: 1-877-PERICOM (1-877-737-4266) FAX: 1-408-435-1100 Internet: http://www.pericom.com ...
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... Semiconductor does not assume any responsibility for use of any circuitry described other than the circuitry embodied in a Pericom Semiconductor product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other rights, of Pericom Semiconductor Corporation. ...
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... This document describes the functionalities of PI7C9X110 (PCI Express Bridge) and provides technical information for designers to design their hardware using PI7C9X110. Pericom Semiconductor – Confidential DESCRIPTION First release of 9X110 datasheet without revision suffix Removed references to PI7C9X110A Revised ESD ratings in “ ...
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... SECONDARY BUS NUMBER REGISTER – OFFSET 18h .................................................................. 36 7.4.13 SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h .............................................................. 36 7.4.14 SECONDARY LATENCY TIME REGISTER – OFFSET 18h................................................................ 36 7.4.15 I/O BASE REGISTER – OFFSET 1Ch.................................................................................................. 36 Pericom Semiconductor – Confidential PCIe-to-PCI Reversible Bridge Page 4 of 144 April 2010, Revision 3.0 PI7C9X110 ...
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... RESERVED REGISTER – OFFSET A8h .............................................................................................. 56 7.4.65 SUBSYSTEM VENDOR ID REGISTER – OFFSET ACh...................................................................... 57 7.4.66 SUBSYSTEM ID REGISTER – OFFSET ACh ...................................................................................... 57 7.4.67 PCI EXPRESS CAPABILITY ID REGISTER – OFFSET B0h .............................................................. 57 Pericom Semiconductor – Confidential PCIe-to-PCI Reversible Bridge Page 5 of 144 April 2010, Revision 3.0 PI7C9X110 ...
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... PORT VC CAPABILITY REGISTER 1 – OFFSET 154h ...................................................................... 71 7.4.117 PORT VC CAPABILITY REGISTER 2 – OFFSET 158h ...................................................................... 71 7.4.118 PORT VC CONTROL REGISTER – OFFSET 15Ch............................................................................. 71 7.4.119 PORT VC STATUS REGISTER – OFFSET 15Ch................................................................................. 71 Pericom Semiconductor – Confidential PCIe-to-PCI Reversible Bridge Page 6 of 144 April 2010, Revision 3.0 PI7C9X110 ...
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... EXPRESS TRANSMITTER/RECEIVER REGISTER – OFFSET 68h.................................................... 91 7.5.42 MEMORY ADDRESS FORWARDING CONTROL REGISTER – OFFSET 68h .................................. 92 7.5.43 UPSTREAM MEMORY WRITE FRAGMENT CONTROL REGISTER – OFFSET 68h ....................... 93 Pericom Semiconductor – Confidential PCIe-to-PCI Reversible Bridge Page 7 of 144 April 2010, Revision 3.0 PI7C9X110 ...
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... UPSTREAM MEMORY 0 TRANSLATED BASE REGISTER – OFFSET E0h .................................... 111 7.5.94 UPSTREAM MEMORY 0 SETUP REGISTER – OFFSET E4h .......................................................... 112 7.5.95 UPSTREAM I/O OR MEMORY 1 TRANSLATED BASE REGISTER – OFFSET E8h ....................... 112 Pericom Semiconductor – Confidential PCIe-to-PCI Reversible Bridge Page 8 of 144 April 2010, Revision 3.0 PI7C9X110 ...
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... RESERVED REGISTERS – OFFSET 01Ch TO 030h ......................................................................... 123 7.6.8 UPSTREAM MEMORY 3 SETUP REGISTER – OFFSET 34h........................................................... 123 7.6.9 UPSTREAM MEMORY 3 UPPER 32-BIT SETUP REGISTER – OFFSET 038h............................... 124 Pericom Semiconductor – Confidential PCIe-to-PCI Reversible Bridge Page 9 of 144 April 2010, Revision 3.0 PI7C9X110 ...
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... BYPASS REGISTER........................................................................................................................................ 135 14.3 DEVICE ID REGISTER................................................................................................................................... 135 14.4 BOUNDARY SCAN REGISTER..................................................................................................................... 135 14.5 JTAG BOUNDARY SCAN REGISTER ORDER ........................................................................................... 135 15 POWER MANAGEMENT .................................................................................................... 138 16 ELECTRICAL AND TIMING SPECIFICATIONS........................................................... 140 Pericom Semiconductor – Confidential Page 10 of 144 April 2010, Revision 3.0 PI7C9X110 PCIe-to-PCI Reversible Bridge ...
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... ABSOLUTE MAXIMUM RATINGS .............................................................................................................. 140 16.2 DC SPECIFICATIONS..................................................................................................................................... 140 16.3 AC SPECIFICATIONS..................................................................................................................................... 141 17 PACKAGE INFORMATION................................................................................................ 142 18 ORDERING INFORMATION.............................................................................................. 143 Pericom Semiconductor – Confidential Page 11 of 144 April 2010, Revision 3.0 PI7C9X110 PCIe-to-PCI Reversible Bridge ...
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... JTAG ID ABLE DEVICE REGISTER T 14-3 JTAG ABLE BOUNDARY SCAR REGISTER DEFINITION T 16-1 A ABLE BSOLUTE MAXIMUM RATINGS T 16-2 DC ABLE ELECTRICAL CHARACTERISTICS T 16-3 PCI ABLE BUS TIMING PARAMETERS Pericom Semiconductor – Confidential ...................................................................................................................................... ............................................................................................ 22 RIDGE ODE B M ...................................................................................................... 23 RIDGE ODE ..................................................................................................................... 141 .................................................................................................................................. 142 ........................................................................................................................... 143 ............................................................................................................................ 25 M (00 – ...................................................................................................... 27 AP ...
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... This page intentionally left blank. Pericom Semiconductor – Confidential Page 13 of 144 April 2010, Revision 3.0 PI7C9X110 PCIe-to-PCI Reversible Bridge ...
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... ASPM support • Beacon support • CRC (16-bit), LCRC (32-bit) • ECRC and advanced error reporting • PRBS (Pseudo Random Bit Sequencing) generator/checker for chip testing Pericom Semiconductor – Confidential PCI Express Port PI7C9X110 PCI 32bit / 66MHz Bus PCI PCI PCI ...
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... EEPROM (I2C) Interface • SM Bus Interface • Auxiliary powers (VAUX, VDDAUX, VDDCAUX) support • Power consumption at about 1.0 Watt in typical condition • Extended commercial/industrial temperature range (-40C to 85C) Pericom Semiconductor – Confidential Page 15 of 144 April 2010, Revision 3.0 PI7C9X110 PCIe-to-PCI Reversible Bridge ...
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... H12, J14, J13, J11, K14 CBE [3:0] C6, A10, C14, G14 PAR B13 FRAME_L B10 Pericom Semiconductor – Confidential TYPE DESCRIPTION I Reference Clock Inputs: Connect to external 100MHz differential clock. These signals require AC coupled with 0.1uF capacitors. I PCI Express data inputs: Differential data receiver input signals ...
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... INTD_L N13 FBCLKIN C2 CLKIN P7 Pericom Semiconductor – Confidential TYPE DESCRIPTION B IRDY (Active LOW): Driven by the initiator of a transaction to indicate its ability to complete current data phase on the primary side. Once asserted in a data phase not de-asserted until the end of the data phase. Before tri-stated driven to a de- asserted state for one cycle ...
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... A1 SDA PME_L A3 CLKRUN_L D3 Pericom Semiconductor – Confidential TYPE DESCRIPTION I Mode Select 2: TM2 is a strapping pin. When TM2 is strapped low for normal operations and strapped high for testing functions. See table 3-1 for mode selection and 3-2 for strapping control for details. ...
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... VAUX B3 AD [31 [29] B5 VSS B6 AD [24 [22] Pericom Semiconductor – Confidential TYPE DESCRIPTION I Reserved 0 Pin: For normal PCI operation, Reserved 0 pin is tied to ground with a capacitor (0.1uF) in parallel. O Reserved 1 Pull-up driver: Don’t care. TYPE DESCRIPTION P Analog Voltage Supply for PCI Express Interface: Connect to the 1.8V Power Supply ...
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... C4 VD33 F14 C5 AD [26 CBE [ VD33 [19 [16] G11 C10 VDDC G12 C11 VSS G13 C12 AD [15] G14 Pericom Semiconductor – Confidential NAME PIN NAME VSS K12 VD33 AD [11] K13 VSS VSS K14 AD [ VDDC VDDAUX L2 VDDCAUX VDDP L3 PERST_L VDDP L4 VD33 AD [8] L5 GNT_L[2]/GPO[0] ...
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... PI7C9X110 is operating in forward (REVRSB=0) and non-transparent bridge mode (TM0=1) shown in Figure 4-1, its PCI Express interface is connected to a root complex and its PCI bus interface is connected to PCI devices. Another example, PI7C9X110 can be configured as a reverse (REVRSB=1) and transparent (TM0=0) bridge shown in Figure 4-2. Pericom Semiconductor – Confidential TM0 CFN_L X ...
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... PCI Host Systems to provide PCI Express capability. PI7C9X110 provides a solution to convert existing PCI based designs to adapt quickly into PCI Express base platforms. Existing PCI based applications will not have to undergo a complete re-architecture in order to interface to PCI Express technology. Pericom Semiconductor – Confidential Host Processor Root ...
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... Figure 4-2 Reverse and Transparent Bridge Mode System Memory PI7C9X110 Pericom Semiconductor – Confidential Host Processor Chipset 32bit / 66MHz Fibre Fast Channel Ethernet x1 link Page 23 of 144 April 2010, Revision 3.0 PI7C9X110 PCIe-to-PCI Reversible Bridge SCSI ...
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... For downstream memory 2, it uses direct address translation. There is no lookup table for downstream memory address translation. Pericom Semiconductor – Confidential Page 24 of 144 April 2010, Revision 3.0 PI7C9X110 ...
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... Upstream Memory 2 Lookup Table (64 32-bit entries) Upstream Memory 3 BAR Upstream Memory 3 Upper 32-bit BAR Upstream Memory 3 Setup Upstream Memory 3 Upper 32-bit Setup Pericom Semiconductor – Confidential Typical access Configuration access offset 10h Configuration access offset 98h Configuration access offset 9Ch Configuration access offset 18h ...
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... When pin REVRSB = 1, device-port type (bit [7:4]) of capability register will be set to 8h (PCI-to-PCI Express bridge). PI7C9X110 supports PCI Express capabilities register structure with capability version set to 1h (bit [3:0] of offset 02h). Pericom Semiconductor – Confidential FMT [0] TLP Format 0 3 double word, without data ...
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... Pericom Semiconductor – Confidential Transparent Mode Non-Transparent (type1) Mode (Type0) Vendor ID Vendor ID Device ID Device ID Command Register ...
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... Pericom Semiconductor – Confidential Transparent Mode Non-Transparent (type1) Mode (Type0) Prefetchable Memory Downstream Memory Limit Register 3 Upper 32-bit BAR Prefetchable Memory ...
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... D3h – D0h D6h – D4h D6h – D4h D7h D7h DBh – D8h DBh – D8h DFh – DCh DFh – DCh Pericom Semiconductor – Confidential Transparent Mode Non-Transparent (type1) Mode (Type0) EEPROM (I2C) EEPROM (I2C) Control and Status Control and status ...
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... Pericom Semiconductor – Confidential Transparent Mode Non-Transparent (type1) Mode (Type0) Reserved Upstream Memory 0 Translated Base Reserved ...
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... Pericom Semiconductor – Confidential Transparent Mode Non-Transparent (type1) Mode (Type0) Secondary Secondary Uncorrectable Error Uncorrectable Error ...
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... PCI CONFIGURATION REGISTERS FOR TRANSPARENT BRIDGE MODE The following section describes the configuration space when the device is in transparent mode. The descriptions for different register type are listed as follow: Register Type RO ROS RW Pericom Semiconductor – Confidential Register Name Reset Value Reserved X Upstream Memory 3 0000_0000h ...
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... VGA Palette Snoop Enable 6 Parity Error Response Enable 7 Wait Cycle Control 8 SERR_L Enable Bit Pericom Semiconductor – Confidential Read/Write “1” to clear Read/Write and Sticky Read/Write “1” to clear and Sticky TYPE DESCRIPTION RO Identifies Pericom as the vendor of this device. Returns 12D8h when read. ...
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... Master Data Parity Error Detected 26:25 DEVSEL_L Timing (medium decode) 27 Signaled Target Abort 28 Received Target Abort Pericom Semiconductor – Confidential TYPE DESCRIPTION Reset Fast back-to-back enable not supported Reset This bit applies to reverse bridge only INTA_L, INTB_L, INTC_L, and INTD_L can be asserted on PCI ...
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... Cache Line Size 3 Cache Line Size 4 Cache Line Size 5 Cache Line Size Pericom Semiconductor – Confidential TYPE DESCRIPTION REVERSE BRIDGE – This bit is set when PI7C9X110 detects a target abort on the primary Reset to 0 RWC FORWARD BRIDGE – This bit is set when PI7C9X110 receives a completion with unsupported request completion status on the primary REVERSE BRIDGE – ...
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... FUNCTION 23:16 Subordinate Bus Number 7.4.14 SECONDARY LATENCY TIME REGISTER – OFFSET 18h BIT FUNCTION 31:24 Secondary Latency Timer 7.4.15 I/O BASE REGISTER – OFFSET 1Ch Pericom Semiconductor – Confidential TYPE DESCRIPTION Reset Bit [7:6] not supported Reset to 00 TYPE DESCRIPTION ...
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... Reserved 23 Fast Back-to-Back Capable 24 Master Data Parity Error Detected 26:25 DEVSEL_L Timing (medium decoding) 27 Signaled Target Abort Pericom Semiconductor – Confidential TYPE DESCRIPTION RO 01: Indicates PI7C9X110 supports 32-bit I/O addressing Reset Reset Indicates the I/O base (0000_0000h) Reset to 0000 TYPE DESCRIPTION ...
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... Addressing Support 15:4 Prefetchable Memory Base 7.4.21 PREFETCHABLE MEMORY LIMIT REGISTER – OFFSET 24h BIT FUNCTION Pericom Semiconductor – Confidential TYPE DESCRIPTION RWC FORWARD BRIDGE – Bit is set when PI7C9X110 detects target abort on the secondary interface REVERSE BRIDGE – ...
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... BIT FUNCTION 19:16 64-bit Addressing Support 31:20 Prefetchable Memory Limit Pericom Semiconductor – Confidential TYPE DESCRIPTION RO 0001: Indicates PI7C9X110 supports 64-bit addressing Reset to 0001 RW Prefetchable Memory Limit (00000000_000FFFFFh) Reset to 000h Page 39 of 144 PI7C9X110 PCIe-to-PCI Reversible Bridge April 2010, Revision 3.0 ...
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... EXPANSION ROM BASE ADDRESS REGISTER – OFFSET 38h BIT FUNCTION 31:0 Expansion ROM Base Address 7.4.28 INTERRUPT LINE REGISTER – OFFSET 3Ch BIT FUNCTION 7:0 Interrupt Line Pericom Semiconductor – Confidential TYPE DESCRIPTION RW Bit [63:32] of prefetchable base Reset to 00000000h TYPE DESCRIPTION RW Bit [63:32] of prefetchable limit Reset to 00000000h ...
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... VGA Enable 20 VGA 16-bit Decode 21 Master Abort Mode 22 Secondary Interface Reset 23 Fast Back-to-Back Enable Pericom Semiconductor – Confidential TYPE DESCRIPTION RO These bits apply to reverse bridge only. Designates interrupt pin INTA_L, is used Reset to 00h when forward mode or 01h when reverse mode. TYPE DESCRIPTION ...
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... Memory Read Prefetching Dynamic Control Disable 2 Completion Data Prediction Control 3 Reserved 5:4 PCI Read Multiple Prefetch Mode Pericom Semiconductor – Confidential TYPE DESCRIPTION RW 0: Primary discard timer counts 2 1: Primary discard timer counts 2 FORWARD BRIDGE – Bit is RO and ignored by the PI7C9X110 Reset ...
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... BIT FUNCTION 15 Flow Control Update Control 16 PCI Retry Counter Status Pericom Semiconductor – Confidential TYPE DESCRIPTION RW 00: Once cache line prefetch if memory read address is in prefetchable range at PCI interface 01: Full prefetch if address is in prefetchable range at PCI interface and the PI7C9X110 will keep remaining data after it is disconnected by an external ...
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... Traffic Class Used For Isochronous Traffic 30 Serial Link Interface Loopback Enable 31 Primary Configuration Access Lockout Pericom Semiconductor – Confidential TYPE DESCRIPTION RW 00: No expiration limit 01: Allow 256 retries before expiration 10: Allow 64K retries before expiration 11: Allow 2G retries before expiration Reset to 00 ...
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... Enable Arbiter 8 7.4.35 ARBITER MODE REGISTER – OFFSET 48h BIT FUNCTION 9 External Arbiter Bit 10 Broken Master Timeout Enable Pericom Semiconductor – Confidential TYPE DESCRIPTION RO Reset to 00000000h TYPE DESCRIPTION RW 0: Disable arbitration for internal PI7C9X110 request 1: Enable arbitration for internal PI7C9X110 request ...
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... Arbiter Priority 4 27 Arbiter Priority 5 28 Arbiter Priority 6 29 Arbiter Priority 7 Pericom Semiconductor – Confidential TYPE DESCRIPTION broken master will be ignored forever after de-asserting its REQ_L for at least 1 clock 1: Refresh broken master state after all the other masters have been served ...
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... Nominal Driver Current Control 5:2 Driver Current Scale Multiple Control 11:8 Driver De-emphasis Level Control 13:12 Transmitter Termination Control Pericom Semiconductor – Confidential TYPE DESCRIPTION RW 0: Low priority request to master 8 1: High priority request to master 8 Reset Reset to 0 TYPE DESCRIPTION RW ...
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... EEPROM 2 EEPROM Error 3 EPROM Autoload Complete Status 5:4 EEPROM Clock Frequency Control 6 EEPROM Autoload Control 7 Fast EEPROM Autoload Control Pericom Semiconductor – Confidential TYPE DESCRIPTION RW 00: 52 ohms 01: 57 ohms 10: 43 ohms 11: 46 ohms Reset Reset to 00h TYPE DESCRIPTION RW Upstream Memory Write Fragment Control ...
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... BIT FUNCTION 8 EEPROM Autoload Status 15:9 EEPROM Word Address 31:16 EEPROM Data Pericom Semiconductor – Confidential TYPE DESCRIPTION RO 0: EEPROM autoload is not on going 1: EEPROM autoload is on going Reset EEPROM word address for EEPROM cycle Reset to 0000000 RW EEPROM data to be written into the EEPROM ...
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... Next Capability Pointer 7.4.47 SECONDARY STATUS REGISTER – OFFSET 80h BIT FUNCTION 16 64-bit Device on Secondary Bus Interface 17 133MHz Capable 18 Split Completion Discarded 19 Unexpected Split Completion Pericom Semiconductor – Confidential TYPE DESCRIPTION RO Reset to 000h RW Reset Reset Reset Reset Reset to 0h TYPE ...
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... Device Number 15:8 Bus Number 16 64-bit Device on Primary Bus Interface 17 133MHz Capable Pericom Semiconductor – Confidential TYPE DESCRIPTION RWC When this bit is set split completion has been terminated by PI7C9X110 with either a retry or disconnect at the next ADB due to the buffer full condition Reset to 0 ...
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... Commitment Limit 7.4.50 DOWNSTREAM SPLIT TRANSACTION REGISTER – OFFSET 8Ch BIT FUNCTION 15:0 Downstream Split Transaction Capability Pericom Semiconductor – Confidential TYPE DESCRIPTION RO / This bit is a read-only and set reverse bridge mode or is read-write in RWC forward bridge mode When this is set split completion has been discarded by PI7C9X110 at ...
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... D1 Power Management 26 D2 Power Management 31:27 PME_L Support Pericom Semiconductor – Confidential TYPE DESCRIPTION RW Downstream Split Transaction Commitment Limit indicates the cumulative sequence size of the commitment limit in units of ADQs. This field can be programmed to any value or equal to the content of the split capability field. ...
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... Capability ID 7.4.58 NEXT POINTER REGISTER – OFFSET A0h BIT FUNCTION 15:8 Next Pointer Pericom Semiconductor – Confidential TYPE DESCRIPTION RW Power State is used to determine the current power state of PI7C9X110 non-implemented state is written to this register, PI7C9X110 will ignore the write data. When present state is D3 and changing to D0 state by ...
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... SECONDARY CLOCK AND CLKRUN CONTROL REGISTER – OFFSET A4h BIT FUNCTION 1:0 S_CLKOUT0 Enable 3:2 S_CLKOUT1 Enable 5:4 S_CLKOUT2 Enable 7:6 S_CLKOUT3 Enable 8 S_CLKOUT4 Enable Pericom Semiconductor – Confidential TYPE DESCRIPTION RW Expansion slot number Reset to 00000 RW First in chassis Reset Reset to 00 TYPE DESCRIPTION ...
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... BIT FUNCTION 15:8 Next Item Pointer 7.4.64 RESERVED REGISTER – OFFSET A8h BIT FUNCTION 31:16 Reserved Pericom Semiconductor – Confidential TYPE DESCRIPTION RW S_CLKOUT (Device 2) Enable for forward bridge mode only 0: enable S_CLKOUT5 1: disable S_CLKOUT5 and driven LOW Reset S_CLKOUT (Device 3) Enable for forward bridge mode only ...
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... Interrupt Message Number 31:30 Reserved 7.4.70 DEVICE CAPABILITY REGISTER – OFFSET B4h BIT FUNCTION 2:0 Maximum Payload Size Pericom Semiconductor – Confidential TYPE DESCRIPTION RO Subsystem vendor ID identifies the particular add-in card or subsystem Reset to 00h TYPE DESCRIPTION RO Subsystem ID identifies the particular add-in card or subsystem ...
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... DEVICE CONTROL REGISTER – OFFSET B8h BIT FUNCTION 0 Correctable Error Reporting Enable 1 Non-Fatal Error Reporting Enable 2 Fatal Error Reporting Enable Pericom Semiconductor – Confidential TYPE DESCRIPTION RO No phantom functions supported Reset 8-bit tag field supported Reset Endpoint L0’s acceptable latency 000: less than 64 ns 001: 64 – ...
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... Detected 20 AUX Power Detected 21 Transaction Pending 31:22 Reserved 7.4.73 LINK CAPABILITY REGISTER – OFFSET BCh BIT FUNCTION Pericom Semiconductor – Confidential TYPE DESCRIPTION RW Reset Relaxed Ordering disabled Reset This field sets the maximum TLP payload size for the PI7C9X110 000: 128 bytes ...
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... Common Clock Configuration 7 Extended Sync 15:8 Reserved 7.4.75 LINK STATUS REGISTER – OFFSET C0h BIT FUNCTION Pericom Semiconductor – Confidential TYPE DESCRIPTION RO Indicates the maximum speed of the Express link 0001: 2.5Gb/s link Reset Indicates the maximum width of the Express link (x1 at reset) ...
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... Physical Slot Number 7.4.77 SLOT CONTROL REGISTER – OFFSET C8h BIT FUNCTION 0 Attention Button Present Enable 1 Power Fault Detected Enable Pericom Semiconductor – Confidential TYPE DESCRIPTION RO This field indicates the negotiated speed of the Express link 001: 2.5Gb/s link Reset 000000: reserved ...
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... XPIP CONFIGURATION REGISTER 2 – OFFSET D4h BIT FUNCTION 7:0 CDR Recovery Time (in the number of FTS order sets) 14:8 L0’s Exit to L0 Latency 15 Reserved 22:16 L1 Exit to L0 Latency 23 Reserved Pericom Semiconductor – Confidential TYPE DESCRIPTION RW Reset Reset Reset Reset Reset Reset to 0 ...
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... Pericom Semiconductor – Confidential Page 63 of 144 April 2010, Revision 3.0 PI7C9X110 PCIe-to-PCI Reversible Bridge ...
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... Reserved 31 VPD Operation 7.4.86 VPD DATA REGISTER – OFFSET DCh BIT FUNCTION 31:0 VPD Data Pericom Semiconductor – Confidential TYPE DESCRIPTION Hot Swap is enabled, this counter is read-write able. This counter is read RW only (RO) if Hot Swap is disabled 00h: 1ms 01h: 2ms ...
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... Reserved 31:2 System Specified Message Address 7.4.92 MESSAGE UPPER ADDRESS REGISTER – OFFSET F8h BIT FUNCTION 31:0 System Specified Message Upper Address Pericom Semiconductor – Confidential TYPE DESCRIPTION RO Reset to 05h TYPE DESCRIPTION RO Next pointer (00h indicates the end of capabilities) Reset to 00h ...
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... BIT FUNCTION 0 Training Error Mast 3:1 Reserved 4 Data Link Protocol Error Mask 11:5 Reserved 12 Poisoned TLP Mask 13 Flow Control Protocol Error Mask Pericom Semiconductor – Confidential TYPE DESCRIPTION RW Reset Reset to 0 TYPE DESCRIPTION RO Reset to 0001h TYPE DESCRIPTION RO Reset to 1h TYPE DESCRIPTION ...
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... Reserved 6 Bad TLP Mask 7 Bad DLLP Mask 8 REPLAY_NUM Rollover Mask 11:9 Reserved 12 Replay Timer Timeout Mask 31:13 Reserved Pericom Semiconductor – Confidential TYPE DESCRIPTION RWS Reset to 0 RWS Reset to 0 RWS Reset to 0 RWS Reset to 0 RWS Reset to 0 RWS Reset to 0 ...
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... Target Abort on Split Completion Status 1 Master Abort on Split Completion Status 2 Received Target Abort Status 3 Received Master Abort Status 4 Reserved 5 Unexpected Split Completion Error Status Pericom Semiconductor – Confidential TYPE DESCRIPTION ROS Reset Reset to 1 RWS Reset Reset to 1 RWS Reset Reset to 0 TYPE ...
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... Target Abort on Split Completion Severity 1 Master Abort on Split Completion Severity 2 Received Target Abort Severity 3 Received Master Abort Severity 4 Reserved Pericom Semiconductor – Confidential TYPE DESCRIPTION RWCS Reset to 0 RWCS Reset to 0 RWCS Reset to 0 RWCS Reset to 0 RWCS Reset to 0 RWCS ...
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... Transaction Address 7.4.112 RESERVED REGISTER – OFFSET 14Ch 7.4.113 VC CAPABILITY ID REGISTER – OFFSET 150h BIT FUNCTION 15:0 VC Capability ID 7.4.114 VC CAPABILITY VERSION REGISTER – OFFSET 150h Pericom Semiconductor – Confidential TYPE DESCRIPTION RWS Reset to 0 RWS Reset to 1 RWS Reset to 0 RWS ...
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... Reject Snoop Transactions 22:16 Maximum Time Slots 23 Reserved 31:24 Port Arbitration Table Offset 7.4.121 VC0 RESOURCE CONTROL REGISTER – OFFSET 164h BIT FUNCTION Pericom Semiconductor – Confidential TYPE DESCRIPTION RO Reset to 1h TYPE DESCRIPTION RO Next capability offset – the end of capabilities Reset to 0 ...
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... Replay Timer 12 Replay Timer Enable 15:13 Reserved 29:16 Acknowledge Latency Timer 30 Acknowledge Latency Timer Enable 31 Reserved 7.4.127 RESERVED REGISTERS – OFFSET 314h – FFCh Pericom Semiconductor – Confidential TYPE DESCRIPTION RO For TC0 Reset For TC7 to TC1 Reset to 7Fh RO Reset Reset ...
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... Bus Master Enable 3 Special Cycle Enable 4 Memory Write and Invalidate Enable 5 VGA Palette Snoop Enable Pericom Semiconductor – Confidential Descriptions Read Only Read Only and Sticky Read/Write Read/Write “1” to clear Read/Write and Sticky Read/Write “1” to clear and Sticky TYPE ...
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... Capable 22 Reserved 23 Fast Back-to-Back Capable Pericom Semiconductor – Confidential TYPE DESCRIPTION RW 0: May ignore any parity error that is detected and take its normal action 1: This bit if set, enables the setting of Master Data Parity Error bit in the Status Register when poisoned TLP received or parity error is detected and ...
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... REVISION ID REGISTER – OFFSET 08h BIT FUNCTION 7:0 Revision 7.5.6 CLASS CODE REGISTER – OFFSET 08h Pericom Semiconductor – Confidential TYPE DESCRIPTION RWC Bit set if its Parity Error Enable bit is set and either of the conditions occurs on the primary: FORWARD BRIDGE – ...
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... Single Function Device 31:24 Reserved 7.5.10 PRIMARY CSR AND MEMORY 0 BASE ADDRESS REGISTER – OFFSET 10h BIT FUNCTION 0 Space Indicator Pericom Semiconductor – Confidential TYPE DESCRIPTION RO Subtractive decoding of PCI-PCI bridge not supported Reset to 00000000 RO Sub-Class Code 10000000: Other bridge Reset to 10000000 ...
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... DOWNSTREAM I/O OR MEMORY 1 BASE ADDRESS REGISTER – OFFSET 18h BIT FUNCTION 0 Space Indicator 2:1 Address Type 3 Prefetchable control 11:4 Reserved 31:12 Base Address Pericom Semiconductor – Confidential TYPE DESCRIPTION Reset 00: 32-bit address decode range 01: 64-bit address decode range 10 and 11: reserved Reset Memory space is non-prefetchable 1: Memory space is prefetchable Reset to 0 ...
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... DOWNSTREAM MEMORY 3 BASE ADDRESS REGISTER – OFFSET 20h BIT FUNCTION 0 Space Indicator 2:1 Address Type 3 Prefetchable control 11:4 Reserved 31:12 Base Address Pericom Semiconductor – Confidential TYPE DESCRIPTION changed to RW. Reset to 00000h TYPE DESCRIPTION RO 0: Memory space 1: IO space Reset 00: 32-bit address decode range ...
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... Primary Interrupt Line 7.5.22 PRIMARY INTERRUPT PIN REGISTER – OFFSET 3Ch BIT FUNCTION Pericom Semiconductor – Confidential TYPE DESCRIPTION RO/RW The size of this Base Address Register is defined from Downstream Memory 3 Upper 32-bit Setup Register (CSR Offset 018h), which can be initialized by EEPROM (I2C Bus or Local Processor ...
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... Primary Interrupt Pin 7.5.23 PRIMARY MINIMUM GRANT REGISTER – OFFSET 3Ch BIT FUNCTION 23:16 Primary Minimum Grant Pericom Semiconductor – Confidential TYPE DESCRIPTION RO These bits apply to reverse bridge only. Designates interrupt pin INTA_L, is used Reset to 00h when forward mode or 01h when reverse mode. ...
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... Reserved 5:4 PCI Read Multiple Prefetch Mode 7:6 PCI Read Line Prefetch Mode Pericom Semiconductor – Confidential TYPE DESCRIPTION RO This register is valid only in reverse bridge mode. It specifies how often that PI7C9X110 needs to gain access to the primary bus in units of ¼ microseconds. Reset to 0 ...
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... Control 16 PCI Retry Counter Status 18:17 PCI Retry Counter Control 19 PCI Discard Timer Disable Pericom Semiconductor – Confidential TYPE DESCRIPTION RW 00: One cache line prefetch if memory read address is in prefetchable range at PCI interface 01: Reserved 10: Full prefetch if memory read address is in prefetchable range at PCI ...
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... BIT FUNCTION 0 I/O Space Enable 1 Memory Space Enable Pericom Semiconductor – Confidential TYPE DESCRIPTION RW 0: Use bit [24] offset 3Ch for forward bridge or bit [25] offset 3Ch for reverse bridge to indicate how many PCI clocks should be allowed before the PCI discard timer expires ...
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... Secondary Interrupt Status 20 Capability List Capable 21 66MHz Capable 22 Reserved Pericom Semiconductor – Confidential TYPE DESCRIPTION not initiate memory or I/O transactions on the secondary interface and disable response to memory and I/O transactions on the secondary interface 1: Enable the PI7C9X110 to operate as a master on the secondary interfaces for memory and I/O transactions forwarded from the secondary interface ...
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... Received Master Abort 30 Signaled System Error 31 Detected Parity Error 7.5.29 ARBITER ENABLE REGISTER – OFFSET 48h Pericom Semiconductor – Confidential TYPE DESCRIPTION RO This bit applies to forward bridge only. 1: Enable fast back-to-back transactions Reset to 0 when reverse bridge or 1 when forward bridge with secondary bus ...
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... BIT FUNCTION 9 External Arbiter Bit 10 Broken Master Timeout Enable 11 Broken Master Refresh Enable Pericom Semiconductor – Confidential TYPE DESCRIPTION RW 0: Disable arbitration for internal PI7C9X110request 1: Enable arbitration for internal PI7C9X110 request Reset Disable arbitration for master 1 1: Enable arbitration for master 1 ...
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... Reserved 7.5.32 SECONDARY CACHE LINE SIZE REGISTER – OFFSET 4Ch BIT FUNCTION Pericom Semiconductor – Confidential TYPE DESCRIPTION RW 08h: These bits are the initialization value of a counter used by the internal arbiter. It controls the number of PCI bus cycles that the arbiter holds a device’ ...
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... SECONDARY CSR AND MEMORY 0 BASE ADDRESS REGISTER – OFFSET 50h BIT FUNCTION 0 Space Indicator 2:1 Address Type 3 Prefetchable control 11:4 Reserved Pericom Semiconductor – Confidential TYPE DESCRIPTION RO 00: Cache line size and 2 DW are not supported Reset Cache line size = 4 double words Reset Cache line size = 8 double words ...
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... Base Address 7.5.38 UPSTREAM MEMORY 2 BASE ADDRESS REGISTER – OFFSET 5Ch BIT FUNCTION 0 Space Indicator Pericom Semiconductor – Confidential TYPE DESCRIPTION RW/RO The size and type of this Base Address Register are defined from Upstream Memory 0 Setup Register (Offset E4h), which can be initialized by EEPROM (I2C Bus or Local Processor ...
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... UPSTREAM MEMORY 3 BASE ADDRESS REGISTER – OFFSET 60h BIT FUNCTION 0 Space Indicator 2:1 Address Type 3 Prefetchable control 11:4 Reserved 31:12 Base Address Pericom Semiconductor – Confidential TYPE DESCRIPTION RO 00: 32-bit address decode range 01, 10 and 11: reserved Reset Memory space is non-prefetchable 1: Memory space is prefetchable Reset Reset to 0 ...
Page 91
... Driver Current Scale Multiple Control 11:8 Driver De-emphasis Level Control Pericom Semiconductor – Confidential TYPE DESCRIPTION RO/RW The size of this Base Address Register is defined from Upstream Memory 3 Upper 32-bit Setup Register (CSR Offset 038h), which can be initialized by EEPROM (I2C Bus or Local Processor. Writing a zero to bit [31] of the setup registers (CSR Offset 038h) to disable this register ...
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... MEMORY ADDRESS FORWARDING CONTROL REGISTER – OFFSET 68h BIT FUNCTION 19:16 Lookup Table Page Size 20 Lookup Table Page Size Extension 21 Upstream 64-bit Address Range Enable 29:22 Reserved Pericom Semiconductor – Confidential TYPE DESCRIPTION RW 00: 52 ohms 01: 57 ohms 10: 43 ohms 11: 46 ohms Reset 00: 52 ohms 01: 57 ohms 10: 43 ohms ...
Page 93
... Control Command for EEPROM 2 EEPROM Error 3 EPROM Autoload Complete Status 5:4 EEPROM Clock Frequency Control 6 EEPROM Autoload Control Pericom Semiconductor – Confidential TYPE DESCRIPTION RW Upstream Memory Write Fragment Control 00: Fragment at 32-byte boundary 01: Fragment at 64-byte boundary 1x: Fragement at 128-byte boundary Reset to 10h TYPE DESCRIPTION RO Subsystem vendor ID identifies the particular add-in card or subsystem ...
Page 94
... SERR_L Forward Enable 3 Secondary Interface Reset 5:4 VGA Enable 6 VGA 16-bit Decode 7 Master Abort Mode 8 Primary Master Timeout Pericom Semiconductor – Confidential TYPE DESCRIPTION RW 0: Normal speed of EEPROM autoload 1: Increase EEPROM autoload by 32x Reset EEPROM autoload is not on going 1: EEPROM autoload is on going Reset to 0 ...
Page 95
... FUNCTION 23:16 Secondary Minimum Grant 7.5.53 SECONDARY MAXIMUM LATENCY TIMER REGISTER – OFFSET 7Ch BIT FUNCTION Pericom Semiconductor – Confidential TYPE DESCRIPTION RW 0: Secondary discard timer counts 215 PCI clock cycles 1: Secondary discard timer counts 210 PCI clock cycles REVERSE BRIDGE – Bit is RO and ignored by PI7C9X110 ...
Page 96
... Split Completion Discarded 19 Unexpected Split Completion 20 Split Completion Overrun 21 Split Request Delayed Pericom Semiconductor – Confidential TYPE DESCRIPTION RO This register is valid only in forward bridge mode. It specifies how often that PI7C9X110 needs to gain access to the primary bus in units of ¼ microseconds. Reset to 0 TYPE ...
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... Capable 18 Split Completion Discarded 19 Unexpected Split Completion Pericom Semiconductor – Confidential TYPE DESCRIPTION RO These bits are only meaningful in forward bridge mode. In reverse bridge mode, all three bits are set to zero. 000: Conventional PCI mode (minimum clock period not applicable) 001: 66MHz (minimum clock period is 15ns) 010: 100 to 133MHz (minimum clock period is 7 ...
Page 98
... Limit 7.5.60 POWER MANAGEMENT ID REGISTER – OFFSET 90h BIT FUNCTION 7:0 Power Management ID Pericom Semiconductor – Confidential TYPE DESCRIPTION RWC When this bit is set split completion has been terminated by PI7C9X110 with either a retry or disconnect at the next ADB due to the buffer full condition ...
Page 99
... PME_L Support 7.5.63 POWER MANAGEMENT CONTROL AND STATUS REGISTER – OFFSET 94h BIT FUNCTION 1:0 Power State 7:2 Reserved Pericom Semiconductor – Confidential TYPE DESCRIPTION RO Next pointer (point to Subsystem ID and Subsystem Vendor ID) Reset to A8h TYPE DESCRIPTION RO Version number that complies with revision 2.0 of the PCI Power Management Interface specification ...
Page 100
... BIT FUNCTION 0 Type Selector 2:1 Address Type 3 Prefetchable Control 11:4 Reserved 30:12 Base Address Register Size Pericom Semiconductor – Confidential TYPE DESCRIPTION RWS 0: PME_L assertion is disabled 1: PME_L assertion is enabled Reset Data register is not implemented Reset to 0000 RO Data register is not implemented Reset to 00 ...
Page 101
... Base Address Register Enable 7.5.67 CAPABILITY ID REGISTER – OFFSET A0h BIT FUNCTION 7:0 Capability ID Pericom Semiconductor – Confidential TYPE DESCRIPTION RO Always set to 1 when a bus master attempts to write a zero to this bit. (WS) PI7C9X110 returns bit [31:12] as FFFFFh (for 4KB size). Reset to 1 TYPE ...
Page 102
... SECONDARY CLOCK AND CLKRUN CONTROL REGISTER – OFFSET A4h BIT FUNCTION 1:0 S_CLKOUT0 Enable 3:2 S_CLKOUT1 Enable 5:4 S_CLKOUT2 Enable 7:6 S_CLKOUT3 Enable Pericom Semiconductor – Confidential TYPE DESCRIPTION RO Next pointer – points to PCI Express capabilities register Reset to B0h TYPE DESCRIPTION RW Expansion slot number Reset to 00000 ...
Page 103
... DONWSTREAM I/O OR MEMORY 1 TRANSLATED BASE REGISTER – OFFSET A8h BIT FUNCTION 5:0 Reserved 31:6 Downstream I/O or Memory 1 Translated Base Pericom Semiconductor – Confidential TYPE DESCRIPTION RW S_CLKOUT (Device 1) Enable for forward bridge mode only 0: enable S_CLKOUT4 1: disable S_CLKOUT4 and driven LOW Reset to 0 ...
Page 104
... PCI EXPRESS CAPABILITY REGISTER – OFFSET B0h BIT FUNCTION 19:16 Capability Version 23:20 Device / Port Type 24 Slot Implemented 29:25 Interrupt Message Number 31:30 Reserved Pericom Semiconductor – Confidential TYPE DESCRIPTION RO 0: Memory space is requested Reset 00: 32-bit address space (WS) 01: 64-bit address space Reset Non-prefetchable ...
Page 105
... Attention Button Present 13 Attention Indicator Present 14 Power Indicator Present 17:15 Reserved 25:18 Captured Slot Power Limit Value Pericom Semiconductor – Confidential TYPE DESCRIPTION RO 000: 128 bytes 001: 256 bytes 010: 512 bytes 011: 1024 bytes 100: 2048 bytes 101: 4096 bytes ...
Page 106
... DEVICE STATUS REGISTER – OFFSET B8h BIT FUNCTION 16 Correctable Error Detected 17 Non-Fatal Error Detected 18 Fatal Error Detected 19 Unsupported Request Detected 20 AUX Power Detected Pericom Semiconductor – Confidential TYPE DESCRIPTION RO This value is set by the Set_Slot_Power_Limit message Reset Reset to 0h TYPE DESCRIPTION RW Reset Reset to 0h ...
Page 107
... ASPM Control 2 Reserved 3 Read Completion Boundary (RCB) 4 Link Disable 5 Retrain Link 6 Common Clock Configuration Pericom Semiconductor – Confidential TYPE DESCRIPTION transaction is pending on transaction layer interface 1: Transaction is pending on transaction layer interface Reset Reset to 0000000000 TYPE DESCRIPTION RO Indicates the maximum speed of the Express link 0001: 2 ...
Page 108
... BIT FUNCTION 7 Extended Sync 15:8 Reserved Pericom Semiconductor – Confidential TYPE DESCRIPTION RW Reset Reset to 00h Page 108 of 144 PI7C9X110 PCIe-to-PCI Reversible Bridge April 2010, Revision 3.0 ...
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... Slot Power Limit Scale 18:17 Reserved 31:19 Physical Slot Number 7.5.84 SLOT CONTROL REGISTER – OFFSET C8h BIT FUNCTION Pericom Semiconductor – Confidential TYPE DESCRIPTION RO This field indicates the negotiated speed of the Express link 001: 2.5Gb/s link Reset 000000: reserved ...
Page 110
... L0’s Lifetime Timer 15:10 Reserved 31:16 L1 Lifetime Timer 7.5.88 XPIP CONFIGURATION REGISTER 2 – OFFSET D4h BIT FUNCTION 7:0 CDR Recovery Time (in the number of FTS order sets) 14:8 L0’s Exit to L0 Latency Pericom Semiconductor – Confidential TYPE DESCRIPTION RW Reset Reset Reset Reset Reset to 0 ...
Page 111
... VPD DATA REGISTER – OFFSET DCh BIT FUNCTION 31:0 VPD Data 7.5.93 UPSTREAM MEMORY 0 TRANSLATED BASE REGISTER – OFFSET E0h BIT FUNCTION 11:0 Reserved 31:12 Downstream Memory 0 Translated Base Pericom Semiconductor – Confidential TYPE DESCRIPTION RO Reset Reset to 19h RO Reset to 0 TYPE DESCRIPTION RO Reset to 03h ...
Page 112
... UPSTREAM I/O OR MEMORY 1 SETUP REGISTER – OFFSET ECh BIT FUNCTION 0 Type Selector 2:1 Address Type 3 Prefetchable Control 5:4 Reserved 30:6 Base Address Register Size Pericom Semiconductor – Confidential TYPE DESCRIPTION RO 0: Memory space is requested Reset 00: 32-bit address space (WS) 01: 64-bit address space Reset Non-prefetchable ...
Page 113
... BIT FUNCTION 31 Base Address Register Enable Pericom Semiconductor – Confidential TYPE DESCRIPTION RO 0: Disable this Base Address Register (WS) 1: Enable this Base Address Register Reset to 0 Page 113 of 144 PI7C9X110 PCIe-to-PCI Reversible Bridge April 2010, Revision 3.0 ...
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... MESSAGE UPPER ADDRESS REGISTER – OFFSET F8h BIT FUNCTION 31:0 System Specified Message Upper Address 7.5.102 MESSAGE DATA REGISTER – OFFSET FCh BIT FUNCTION Pericom Semiconductor – Confidential TYPE DESCRIPTION RO Reset to 05h TYPE DESCRIPTION RO Next pointer (00h indicates the end of capabilities) ...
Page 115
... Reserved 4 Data Link Protocol Error Mask 11:5 Reserved 12 Poisoned TLP Mask 13 Flow Control Protocol Error Mask 14 Completion Timeout Mask 15 Completion Abort Mask Pericom Semiconductor – Confidential TYPE DESCRIPTION RW Reset Reset to 0 TYPE DESCRIPTION RO Reset to 0001h TYPE DESCRIPTION RO Reset to 1h TYPE ...
Page 116
... Reserved 6 Bad TLP Mask 7 Bad DLLP Mask 8 REPLAY_NUM Rollover Mask 11:9 Reserved 12 Replay Timer Timeout Mask 31:13 Reserved Pericom Semiconductor – Confidential TYPE DESCRIPTION RWS Reset to 0 RWS Reset to 0 RWS Reset to 0 RWS Reset to 0 RWS Reset Reset to 0 TYPE ...
Page 117
... Target Abort on Split Completion Status 1 Master Abort on Split Completion Status 2 Received Target Abort Status 3 Received Master Abort Status 4 Reserved 5 Unexpected Split Completion Error Status Pericom Semiconductor – Confidential TYPE DESCRIPTION ROS Reset Reset to 1 RWS Reset Reset to 1 RWS Reset Reset to 0 TYPE ...
Page 118
... Target Abort on Split Completion Severity 1 Master Abort on Split Completion Severity 2 Received Target Abort Severity 3 Received Master Abort Severity 4 Reserved Pericom Semiconductor – Confidential TYPE DESCRIPTION RWCS Reset to 0 RWCS Reset to 0 RWCS Reset to 0 RWCS Reset to 0 RWCS Reset to 0 RWCS ...
Page 119
... Transaction Address 7.5.121 RESERVED REGISTER – OFFSET 14Ch 7.5.122 VC CAPABILITY ID REGISTER – OFFSET 150h BIT FUNCTION 15:0 VC Capability ID 7.5.123 VC CAPABILITY VERSION REGISTER – OFFSET 150h Pericom Semiconductor – Confidential TYPE DESCRIPTION RWS Reset to 0 RWS Reset to 1 RWS Reset to 0 RWS ...
Page 120
... Reject Snoop Transactions 22:16 Maximum Time Slots 23 Reserved 31:24 Port Arbitration Table Offset 7.5.130 VC0 RESOURCE CONTROL REGISTER – OFFSET 164h BIT FUNCTION Pericom Semiconductor – Confidential TYPE DESCRIPTION RO Reset to 1h TYPE DESCRIPTION RO Next capability offset – the end of capabilities Reset to 0 ...
Page 121
... Replay Timer 12 Replay Timer Enable 15:13 Reserved 29:16 Acknowledge Latency Timer 30 Acknowledge Latency Timer Enable 31 Reserved 7.5.136 RESERVED REGISTERS – OFFSET 314h – FFCh Pericom Semiconductor – Confidential TYPE DESCRIPTION RO For TC0 Reset For TC7 to TC1 Reset to 7Fh RO Reset Reset ...
Page 122
... Base Address Register Enable 7.6.4 DOWNSTREAM MEMORY 3 TRANSLATED BASE REGISTER – OFFSET 010h BIT FUNCTION 11:0 Reserved Pericom Semiconductor – Confidential Descriptions Read Only Read Only and Sticky Read/Write Read/Write “1” to clear Read/Write and Sticky Read/Write “1” to clear and Sticky ...
Page 123
... BIT FUNCTION 0 Type Selector 2:1 Address Type Pericom Semiconductor – Confidential TYPE DESCRIPTION RW Define the translated base address for downstream memory transactions whose initiator addresses fall into Downstream Memory 3 address range. The number of bits that are used for translated base is determined by its setup ...
Page 124
... LOOKUP TABLE DATA – OFFSET 054h BIT FUNCTION 0 Valid 2:1 Reserved 3 Prefetchable 7:4 Reserved Pericom Semiconductor – Confidential TYPE DESCRIPTION RW 0: Non-prefetchable 1: Prefetchable Reset Reset Set the corresponding bit in the Base Address Register to read only 1: Set the corresponding bit in the Base Address Register to read/write in ...
Page 125
... UPSTREAM PAGE BOUNDARY IRQ 1 REQUEST REGISTER – OFFSET 05Ch BIT FUNCTION 31:0 Upstream Page Boundary IRQ 1 Pericom Semiconductor – Confidential TYPE DESCRIPTION RW/RO Data written or read from the Lookup Table at the offset specified in the Lookup Table Offset Register. When writing to this register, the data value is written to the specified Lookup Table entry ...
Page 126
... Primary Clear IRQ 7.6.19 SECONDARY CLEAR IRQ REGISTER – OFFSET 070h BIT FUNCTION 31:16 Secondary Clear IRQ Pericom Semiconductor – Confidential TYPE DESCRIPTION RWC 0: PI7C9X110 can initiate an interrupt request when the correspondent request bit is set 1: PI7C9X110 cannot initiate any interrupt request even though the ...
Page 127
... Primary Clear IRQ Mask 7.6.23 SECONDARY CLEAR IRQ MASK REGISTER – OFFSET 078h BIT FUNCTION 31:16 Secondary Clear IRQ Mask Pericom Semiconductor – Confidential TYPE DESCRIPTION RWS When writing “1” to this register bit, it set the correspondent interrupt request bit. When reading this register, it returns the interrupt request bit status: ...
Page 128
... Scratchpad 0 7.6.28 SCRATCHPAD 1 REGISTER – OFFSET 0A4h BIT FUNCTION 31:0 Scratchpad 1 Pericom Semiconductor – Confidential TYPE DESCRIPTION RWS When writing “1” to this register bit, it set the correspondent interrupt request mask bit. When reading this register, it returns the Primary Set IRQ Mask bit status: ...
Page 129
... Scratchpad 5 7.6.33 SCRATCHPAD 6 REGISTER – OFFSET 0B8h BIT FUNCTION 31:0 Scratchpad 6 Pericom Semiconductor – Confidential TYPE DESCRIPTION RW The scratchpad is a 32-bit internal register that can be accessed from both primary and secondary interfaces. The external devices can use the scratchpad as a temporary storage. Primary and secondary bus devices can communicate through the scratchpad ...
Page 130
... LOOKUP TABLE REGISTERS – OFFSET 100h TO 1FCh BIT FUNCTION 2047:0 Lookup Table 7.6.37 RESERVED REGISTERS – OFFSET 200h TO FFCh Pericom Semiconductor – Confidential TYPE DESCRIPTION RW The scratchpad is a 32-bit internal register that can be accessed from both primary and secondary interfaces. The external devices can use the scratchpad as a temporary storage ...
Page 131
... GPIO[0] : PCI slot Card Presence Detection Input GPIO[1] : Attention Button Pressed Input GPIO[2] : Power Indication Output GPIO[3] : Attention Indication Output In Reverse Mode: GPIO[0] : PCIe slot Card Presence Detection Input GPIO[1] : MRL Sensor Input GPIO[2] : Reserved GPIO[3] : Reserved Pericom Semiconductor – Confidential SM Bus device GPIO [3] = GPIO [2] = GPIO [1] = GPIO [0] ...
Page 132
... Table 10-2 PCI interrupt to PCIe interrupt message mapping in forward bridge mode PCI Interrupts (from sources of interrupts) INTA INTB INTC INTD 11 EEPROM (I2C) INTERFACE AND SYSTEM MANAGEMENT BUS Pericom Semiconductor – Confidential PCI Interrupts (to host controller) INTA INTB INTC INTD PCIe Interrupt message packets (to host controller) INTA message ...
Page 133
... PRSNT1# and PRSNT2# are not implemented on both PI7C9X110. The use of these two signals is mandatory on an add-in card in order to support hot-plug. 13 RESET SCHEME Pericom Semiconductor – Confidential Page 133 of 144 PI7C9X110 PCIe-to-PCI Reversible Bridge April 2010, Revision 3.0 ...
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... Test Clock (TCK) and the Test Mode Select (TMS) pins. An independent power on reset circuit is provided to ensure the machine is in TEST_LOGIC_RESET state at power-up. The JTAG signal lines are not active when the PCI resource is operating PCI bus cycles. 14.1 INSTRUCTION REGISTER Pericom Semiconductor – Confidential Page 134 of 144 PI7C9X110 PCIe-to-PCI Reversible Bridge ...
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... SAMPLE and EXTEST instructions. Parallel loading takes place on the rising edge of TCK. 14.5 JTAG BOUNDARY SCAN REGISTER ORDER Table 14-3 JTAG boundary scar register definition Pericom Semiconductor – Confidential Register Selected Operation Boundary Scan ...
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... LOCK_L STOP_L DEVSEL_L TRDY_L 49 IRDY_L FRAME_L CBE [ [16 [17 [18] Pericom Semiconductor – Confidential Ball Location Type K14 BIDIR - CONTROL J11 BIDIR - CONTROL J13 BIDIR - CONTROL J14 BIDIR - CONTROL H12 BIDIR - CONTROL H13 BIDIR - CONTROL G11 BIDIR - CONTROL G12 BIDIR - CONTROL G14 BIDIR ...
Page 137
... REQ_L [4] 108 REQ_L [5] 109 REQ_L [6] 110 REQ_L [7] 111 INTA_L 112 - 113 GNT_L [0] 114 - 115 GNT_L [1] 116 GNT_L [2] 117 GNT_L [3] 118 GNT_L [4] 119 GNT_L [5] Pericom Semiconductor – Confidential Ball Location Type - CONTROL C8 BIDIR - CONTROL A8 BIDIR - CONTROL D7 BIDIR - CONTROL B7 BIDIR - CONTROL A7 BIDIR - CONTROL ...
Page 138
... PCIe devices to the PME_L signal and continues to request power management state change to the host bridge. PI7C9X110 also supports ASPM (Active State Power Management) to facilitate the link power saving. PI7C9X110 supports Beacon generation but does not support WAKE# signal. Pericom Semiconductor – Confidential Ball Location P6 N6 ...
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... Pericom Semiconductor – Confidential Page 139 of 144 PI7C9X110 PCIe-to-PCI Reversible Bridge April 2010, Revision 3.0 ...
Page 140
... By the same token, VD33/VDDC and VAUX/VDDCAUX need to be separated for auxiliary power management support. However, if auxiliary power management is not required, VD33 and VDDC can be connected to VAUX and VDDCAUX respectively. The typical power consumption of PI7C9X110 is about 1.0 watt. Pericom Semiconductor – Confidential o -65 o -40 -0 ...
Page 141
... Point-to-point signals are REQ_L [7:0], GNT_L [7:0], LOO, and ENUM_L. Bused signals are AD, CBE, PAR, PERR_L, SERR_L, FRAME_L, IRDY_L, TRDY_L, LOCK_L, STOP_L and IDSEL. 4. REQ_L signals have a setup of 10ns and GNT_L signals have a setup of 12ns. Figure 16-1 PCI signal timing conditions Pericom Semiconductor – Confidential 66 MHz MIN 1,2,3 ...
Page 142
... PACKAGE INFORMATION Figure 17-1 Top view drawing Figure 17-2 Bottom view drawing Pericom Semiconductor – Confidential Page 142 of 144 PI7C9X110 PCIe-to-PCI Reversible Bridge April 2010, Revision 3.0 ...
Page 143
... The package of PI7C9X110 is a 12mm x 12mm LFBGA (160 Pin) package. The ball pitch is 0.8mm and the ball size is 0.5mm. The following are the package information and mechanical dimension: Figure 17-3 Package outline drawing 18 ORDERING INFORMATION PART NUMBER PIN – PACKAGE PI7C9X110BNBE 160 – LFBGA PI7C9X110BNB 160 – LFBGA Pericom Semiconductor – Confidential PB-FREE & GREEN TEMPERATURE RANGE ...
Page 144
... NOTES: Pericom Semiconductor – Confidential Page 144 of 144 PI7C9X110 PCIe-to-PCI Reversible Bridge April 2010, Revision 3.0 ...