PI7C9X110BNBE Pericom Semiconductor, PI7C9X110BNBE Datasheet - Page 10

• Manufacturer Part Number: PI7C9X110BNBE
• Description: IC PCIE TO PCI REV BRG 160LFBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X110BNBE

• Applications: PCI-to-PCI Bridge
• Interface: I²C
• Voltage - Supply: 1.8 V
• Package / Case: 160-LBGA
• Mounting Type: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Rad Hardened: No
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Compliant

8
9
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11
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11.1
11.2
14.1
14.2
14.3
14.4
14.5
7.6.10
7.6.11
7.6.12
7.6.13
7.6.14
7.6.15
7.6.16
7.6.17
7.6.18
7.6.19
7.6.20
7.6.21
7.6.22
7.6.23
7.6.24
7.6.25
7.6.26
7.6.27
7.6.28
7.6.29
7.6.30
7.6.31
7.6.32
7.6.33
7.6.34
7.6.35
7.6.36
7.6.37
GPIO PINS AND SM BUS ADDRESS..................................................................................... 131
CLOCK SCHEME ..................................................................................................................... 132
Pericom Semiconductor – Confidential
INTERRUPTS......................................................................................................................... 132
EEPROM (I2C) INTERFACE AND SYSTEM MANAGEMENT BUS ........................... 132
HOT PLUG OPERATION .................................................................................................... 133
RESET SCHEME................................................................................................................... 133
IEEE 1149.1 COMPATIBLE JTAG CONTROLLER ....................................................... 134
POWER MANAGEMENT .................................................................................................... 138
ELECTRICAL AND TIMING SPECIFICATIONS........................................................... 140
EEPROM (I2C) INTERFACE .......................................................................................................................... 133
SYSTEM MANAGEMENT BUS..................................................................................................................... 133
INSTRUCTION REGISTER ............................................................................................................................ 134
BYPASS REGISTER........................................................................................................................................ 135
DEVICE ID REGISTER................................................................................................................................... 135
BOUNDARY SCAN REGISTER..................................................................................................................... 135
JTAG BOUNDARY SCAN REGISTER ORDER ........................................................................................... 135
RESERVED REGISTERS – OFFSET 03Ch TO 04Ch ........................................................................ 124
LOOKUP TABLE OFFSET – OFFSET 050h ..................................................................................... 124
LOOKUP TABLE DATA – OFFSET 054h.......................................................................................... 124
UPSTREAM PAGE BOUNDARY IRQ 0 REQUEST REGISTER – OFFSET 058h ............................ 125
UPSTREAM PAGE BOUNDARY IRQ 1 REQUEST REGISTER – OFFSET 05Ch............................ 125
UPSTREAM PAGE BOUNDARY IRQ 0 MASK REGISTER – OFFSET 060h ................................... 126
UPSTREAM PAGE BOUNDARY IRQ 1 MASK REGISTER – OFFSET 064h ................................... 126
RESERVED REGISTER – OFFSET 068C .......................................................................................... 126
PRIMARY CLEAR IRQ REGISTER – OFFSET 070h......................................................................... 126
SECONDARY CLEAR IRQ REGISTER – OFFSET 070h................................................................... 126
PRIMARY SET IRQ REGISTER – OFFSET 074h .............................................................................. 127
SECONDARY SET IRQ REGISTER – OFFSET 074h ........................................................................ 127
PRIMARY CLEAR IRQ MASK REGISTER – OFFSET 078h ............................................................. 127
SECONDARY CLEAR IRQ MASK REGISTER – OFFSET 078h ....................................................... 127
PRIMARY SET IRQ MASK REGISTER – OFFSET 07Ch .................................................................. 128
SECONDARY SET IRQ MASK REGISTER – OFFSET 07Ch ............................................................ 128
RESERVED REGISTERS – OFFSET 080h TO 09Ch ......................................................................... 128
SCRATCHPAD 0 REGISTER – OFFSET 0A0h.................................................................................. 128
SCRATCHPAD 1 REGISTER – OFFSET 0A4h.................................................................................. 128
SCRATCHPAD 2 REGISTER – OFFSET 0A8h.................................................................................. 129
SCRATCHPAD 3 REGISTER – OFFSET 0ACh ................................................................................. 129
SCRATCHPAD 4 REGISTER – OFFSET 0B0h.................................................................................. 129
SCRATCHPAD 5 REGISTER – OFFSET 0B4h.................................................................................. 129
SCRATCHPAD 6 REGISTER – OFFSET 0B8h.................................................................................. 129
SCRATCHPAD 7 REGISTER – OFFSET 0BCh ................................................................................. 130
RESERVED REGISTERS – OFFSET 0C0h TO 0FCh........................................................................ 130
LOOKUP TABLE REGISTERS – OFFSET 100h TO 1FCh ............................................................... 130
RESERVED REGISTERS – OFFSET 200h TO FFCh ........................................................................ 130
Page 10 of 144
April 2010, Revision 3.0
PCIe-to-PCI Reversible Bridge
PI7C9X110