PI7C9X110BNBE Pericom Semiconductor, PI7C9X110BNBE Datasheet - Page 8

• Manufacturer Part Number: PI7C9X110BNBE
• Description: IC PCIE TO PCI REV BRG 160LFBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X110BNBE

• Applications: PCI-to-PCI Bridge
• Interface: I²C
• Voltage - Supply: 1.8 V
• Package / Case: 160-LBGA
• Mounting Type: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Rad Hardened: No
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Compliant

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Pericom Semiconductor – Confidential
SUBSYSTEM VENDOR ID REGISTER – OFFSET 6Ch ...................................................................... 93
SUBSYSTEM ID REGISTER – OFFSET 6Ch....................................................................................... 93
EEPROM AUTOLOAD CONTROL/STATUS REGISTER – OFFSET 70h........................................... 93
RESERVED REGISTER – OFFSET 74h............................................................................................... 94
BRIDGE CONTROL AND STATUS REGISTER – OFFSET 78h ......................................................... 94
GPIO DATA AND CONTROL REGISTER – OFFSET 78h.................................................................. 95
SECONDARY INTERRUPT LINE REGISTER – OFFSET 7Ch ........................................................... 95
SECONDARY INTERRUPT PIN REGISTER – OFFSET 7Ch.............................................................. 95
SECONDARY MINIMUM GRANT REGISTER – OFFSET 7Ch .......................................................... 95
SECONDARY MAXIMUM LATENCY TIMER REGISTER – OFFSET 7Ch......................................... 95
NEXT CAPABILITY POINTER REGISTER – OFFSET 80h ................................................................ 96
UPSTREAM SPLIT TRANSACTION REGISTER – OFFSET 88h ........................................................ 98
DOWNSTREAM SPLIT TRANSACTION REGISTER – OFFSET 8Ch ................................................. 98
POWER MANAGEMENT ID REGISTER – OFFSET 90h.................................................................... 98
NEXT CAPABILITY POINTER REGISTER – OFFSET 90h ................................................................ 99
POWER MANAGEMENT CAPABILITY REGISTER – OFFSET 90h .................................................. 99
POWER MANAGEMENT CONTROL AND STATUS REGISTER – OFFSET 94h .............................. 99
PCI-TO-PCI SUPPORT EXTENSION REGISTER – OFFSET 94h ................................................... 100
DOWNSTREAM MEMORY 0 TRANSLATED BASE REGISTER – OFFSET 98h .............................. 100
DOWNSTREAM MEMORY 0 SETUP REGISTER – OFFSET 9Ch ................................................... 100
CAPABILITY ID REGISTER – OFFSET A0h..................................................................................... 101
NEXT POINTER REGISTER – OFFSET A0h..................................................................................... 102
SLOT NUMBER REGISTER – OFFSET A0h ..................................................................................... 102
CHASSIS NUMBER REGISTER – OFFSET A0h ............................................................................... 102
SECONDARY CLOCK AND CLKRUN CONTROL REGISTER – OFFSET A4h............................... 102
DONWSTREAM I/O OR MEMORY 1 TRANSLATED BASE REGISTER – OFFSET A8h ................. 103
DOWSTREAM I/O OR MEMORY 1 SETUP REGISTER – OFFSET ACh ......................................... 104
PCI EXPRESS CAPABILITY ID REGISTER – OFFSET B0h ............................................................ 104
NEXT CAPABILITY POINTER REGISTER – OFFSET B0h .............................................................. 104
PCI EXPRESS CAPABILITY REGISTER – OFFSET B0h ................................................................. 104
DEVICE CAPABILITY REGISTER – OFFSET B4h........................................................................... 105
DEVICE CONTROL REGISTER – OFFSET B8h............................................................................... 106
DEVICE STATUS REGISTER – OFFSET B8h................................................................................... 106
LINK CAPABILITY REGISTER – OFFSET BCh ............................................................................... 107
LINK CONTROL REGISTER – OFFSET C0h.................................................................................... 107
LINK STATUS REGISTER – OFFSET C0h........................................................................................ 109
SLOT CAPABILITY REGISTER – OFFSET C4h ............................................................................... 109
SLOT CONTROL REGISTER – OFFSET C8h ................................................................................... 109
SLOT STATUS REGISTER – OFFSET C8h ....................................................................................... 110
XPIP CONFIGURATION REGISTER 0 – OFFSET CCh................................................................... 110
XPIP CONFIGURATION REGISTER 1 – OFFSET D0h ................................................................... 110
XPIP CONFIGURATION REGISTER 2 – OFFSET D4h ................................................................... 110
CAPABILITY ID REGISTER – OFFSET D8h .................................................................................... 111
NEXT POINTER REGISTER – OFFSET D8h .................................................................................... 111
VPD REGISTER – OFFSET D8h ....................................................................................................... 111
VPD DATA REGISTER – OFFSET DCh............................................................................................ 111
UPSTREAM MEMORY 0 TRANSLATED BASE REGISTER – OFFSET E0h .................................... 111
UPSTREAM MEMORY 0 SETUP REGISTER – OFFSET E4h .......................................................... 112
UPSTREAM I/O OR MEMORY 1 TRANSLATED BASE REGISTER – OFFSET E8h ....................... 112
CAPABILITY ID REGISTER – OFFSET 80h ...................................................................................... 96
SECONDARY STATUS REGISTER – OFFSET 80h............................................................................ 96
BRIDGE STATUS REGISTER – OFFSET 84h .................................................................................... 97
Page 8 of 144
April 2010, Revision 3.0
PCIe-to-PCI Reversible Bridge
PI7C9X110