PI7C9X110BNBE Pericom Semiconductor, PI7C9X110BNBE Datasheet - Page 53

• Manufacturer Part Number: PI7C9X110BNBE
• Description: IC PCIE TO PCI REV BRG 160LFBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X110BNBE

• Applications: PCI-to-PCI Bridge
• Interface: I²C
• Voltage - Supply: 1.8 V
• Package / Case: 160-LBGA
• Mounting Type: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Rad Hardened: No
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Compliant

7.4.51 POWER MANAGEMENT ID REGISTER – OFFSET 90h
7.4.52 NEXT CAPABILITY POINTER REGISTER – OFFSET 90h
7.4.53 POWER MANAGEMENT CAPABILITY REGISTER – OFFSET 90h
Pericom Semiconductor – Confidential
BIT
31:16
BIT
7:0
BIT
15:8
BIT
18:16
19
20
21
24:22
25
26
31:27
FUNCTION
Downstream Split
Transaction Commitment
Limit
FUNCTION
Power Management ID
FUNCTION
Next Pointer
FUNCTION
Version Number
PME Clock
Reserved
Device Specific Initialization
(DSI)
AUX Current
D1 Power Management
D2 Power Management
PME_L Support
TYPE
TYPE
TYPE
TYPE
RW
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
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DESCRIPTION
Downstream Split Transaction Commitment Limit indicates the cumulative
sequence size of the commitment limit in units of ADQs. This field can be
programmed to any value or equal to the content of the split capability field.
For example, if the limit is set to FFFFh, PI7C9X110 is allowed to forward
all split requests of any size regardless of the amount of buffer space
available. The split transaction commitment limit is set to 0010h that is the
same value as the split transaction capability.
Reset to 0010h
DESCRIPTION
Power Management ID Register
Reset to 01h
DESCRIPTION
Next pointer (point to Subsystem ID and Subsystem Vendor ID)
Reset to A8h
DESCRIPTION
Version number that complies with revision 2.0 of the PCI Power
Management Interface specification.
Reset to 010
PME clock is not required for PME_L generation
Reset to 0
Reset to 0
DSI – no special initialization of this function beyond the standard PCI
configuration header is required following transition to the D0 un-initialized
state
Reset to 0
000: 0mA
001: 55mA
010: 100mA
011: 160mA
100: 220mA
101: 270mA
110: 320mA
111: 375mA
Reset to 001
D1 power management is not supported
Reset to 0
D2 power management is not supported
Reset to 0
PME_L is supported in D3 cold, D3 hot, and D0 states.
Reset to 11001
April 2010, Revision 3.0
PCIe-to-PCI Reversible Bridge
PI7C9X110