PI7C9X110BNBE Pericom Semiconductor, PI7C9X110BNBE Datasheet - Page 5

• Manufacturer Part Number: PI7C9X110BNBE
• Description: IC PCIE TO PCI REV BRG 160LFBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X110BNBE

• Applications: PCI-to-PCI Bridge
• Interface: I²C
• Voltage - Supply: 1.8 V
• Package / Case: 160-LBGA
• Mounting Type: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Rad Hardened: No
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Compliant

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Pericom Semiconductor – Confidential
I/O LIMIT REGISTER – OFFSET 1Ch................................................................................................. 37
SECONDARY STATUS REGISTER – OFFSET 1Ch ............................................................................ 37
MEMORY BASE REGISTER – OFFSET 20h ....................................................................................... 38
MEMORY LIMIT REGISTER – OFFSET 20h ...................................................................................... 38
PREFETCHABLE MEMORY BASE REGISTER – OFFSET 24h......................................................... 38
PREFETCHABLE MEMORY LIMIT REGISTER – OFFSET 24h........................................................ 38
PREFETCHABLE BASE UPPER 32-BIT REGISTER – OFFSET 28h................................................. 40
PREFETCHABLE LIMIT UPPER 32-BIT REGISTER – OFFSET 2Ch............................................... 40
I/O BASE UPPER 16-BIT REGISTER – OFFSET 30h......................................................................... 40
I/O LIMIT UPPER 16-BIT REGISTER – OFFSET 30h........................................................................ 40
CAPABILITY POINTER – OFFSET 34h .............................................................................................. 40
EXPANSION ROM BASE ADDRESS REGISTER – OFFSET 38h ....................................................... 40
INTERRUPT LINE REGISTER – OFFSET 3Ch................................................................................... 40
INTERRUPT PIN REGISTER – OFFSET 3Ch ..................................................................................... 41
BRIDGE CONTROL REGISTER – OFFSET 3Ch ................................................................................ 41
PCI DATA BUFFERING CONTROL REGISTER – OFFSET 40h ....................................................... 42
CHIP CONTROL 0 REGISTER – OFFSET 40h................................................................................... 43
RESERVED REGISTER – OFFSET 44h............................................................................................... 45
ARBITER ENABLE REGISTER – OFFSET 48h................................................................................... 45
ARBITER MODE REGISTER – OFFSET 48h...................................................................................... 45
ARBITER PRIORITY REGISTER – OFFSET 48h ................................................................................ 46
RESERVED REGISTERS – OFFSET 4Ch – 64h .................................................................................. 47
EXPRESS TRANSMITTER/RECEIVER REGISTER – OFFSET 68h.................................................... 47
UPSTREAM MEMORY WRITE FRAGMENT CONTROL REGISTER – OFFSET 68h ....................... 48
RESERVED REGISTER – OFFSET 6Ch .............................................................................................. 48
EEPROM AUTOLOAD CONTROL/STATUS REGISTER – OFFSET 70h........................................... 48
RESERVED REGISTER – OFFSET 74h............................................................................................... 50
GPIO DATA AND CONTROL REGISTER – OFFSET 78h.................................................................. 50
RESERVED REGISTER – OFFSET 7Ch .............................................................................................. 50
NEXT CAPABILITY POINTER REGISTER – OFFSET 80h ................................................................ 50
UPSTREAM SPLIT TRANSACTION REGISTER – OFFSET 88h ........................................................ 52
DOWNSTREAM SPLIT TRANSACTION REGISTER – OFFSET 8Ch ................................................. 52
POWER MANAGEMENT ID REGISTER – OFFSET 90h.................................................................... 53
NEXT CAPABILITY POINTER REGISTER – OFFSET 90h ................................................................ 53
POWER MANAGEMENT CAPABILITY REGISTER – OFFSET 90h .................................................. 53
POWER MANAGEMENT CONTROL AND STATUS REGISTER – OFFSET 94h .............................. 54
PCI-TO-PCI SUPPORT EXTENSION REGISTER – OFFSET 94h ..................................................... 54
RESERVED REGISTERS – OFFSET 98h – 9Ch .................................................................................. 54
CAPABILITY ID REGISTER – OFFSET A0h....................................................................................... 54
NEXT POINTER REGISTER – OFFSET A0h....................................................................................... 54
SLOT NUMBER REGISTER – OFFSET A0h ....................................................................................... 55
CHASSIS NUMBER REGISTER – OFFSET A0h ................................................................................. 55
SECONDARY CLOCK AND CLKRUN CONTROL REGISTER – OFFSET A4h................................. 55
CAPABILITY ID REGISTER – OFFSET A8h....................................................................................... 56
NEXT POINTER REGISTER – OFFSET A8h....................................................................................... 56
RESERVED REGISTER – OFFSET A8h .............................................................................................. 56
SUBSYSTEM VENDOR ID REGISTER – OFFSET ACh...................................................................... 57
SUBSYSTEM ID REGISTER – OFFSET ACh ...................................................................................... 57
PCI EXPRESS CAPABILITY ID REGISTER – OFFSET B0h .............................................................. 57
CAPABILITY ID REGISTER – OFFSET 80h ...................................................................................... 50
SECONDARY STATUS REGISTER – OFFSET 80h............................................................................ 50
BRIDGE STATUS REGISTER – OFFSET 84h .................................................................................... 51
Page 5 of 144
April 2010, Revision 3.0
PCIe-to-PCI Reversible Bridge
PI7C9X110