PI7C9X110BNBE Pericom Semiconductor, PI7C9X110BNBE Datasheet - Page 87

• Manufacturer Part Number: PI7C9X110BNBE
• Description: IC PCIE TO PCI REV BRG 160LFBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X110BNBE

• Applications: PCI-to-PCI Bridge
• Interface: I²C
• Voltage - Supply: 1.8 V
• Package / Case: 160-LBGA
• Mounting Type: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Rad Hardened: No
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Compliant

7.5.31 ARBITER PRIORITY REGISTER – OFFSET 48h
7.5.32 SECONDARY CACHE LINE SIZE REGISTER – OFFSET 4Ch
Pericom Semiconductor – Confidential
BIT
19:12
20
21
BIT
22
23
24
25
26
27
28
29
30
31
BIT
FUNCTION
Arbiter Fairness Counter
GNT_L Output Toggling
Enable
Reserved
FUNCTION
Arbiter Priority 0
Arbiter Priority 1
Arbiter Priority 2
Arbiter Priority 3
Arbiter Priority 4
Arbiter Priority 5
Arbiter Priority 6
Arbiter Priority 7
Arbiter Priority 8
Reserved
FUNCTION
TYPE
TYPE
TYPE
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
RO
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DESCRIPTION
08h: These bits are the initialization value of a counter used by the internal
arbiter. It controls the number of PCI bus cycles that the arbiter holds a
device’s PCI bus GNT active after detecting a PCI bus REQ_L from another
device. The counter is reloaded whenever a new PCI bus GNT is asserted.
For every new PCI bus GNT, the counter is armed to decrement when it
detects the new fall of FRAME_L. If the arbiter fairness counter is set to 00h,
the arbiter will not remove a device’s PCI bus GNT until the device has de-
asserted its PCI bus REQ.
Reset to 08h
0: GNT_L not de-asserted after granted master assert FRAME_L
1: GNT_L de-asserts for 1 clock after 2 clocks of the granted master asserting
FRAME_L
Reset to 0
Reset to 0
DESCRIPTION
0: Low priority request to internal PI7C9X110
1: High priority request to internal PI7C9X110
Reset to 1
0: Low priority request to master 1
1: High priority request to master 1
Reset to 0
0: Low priority request to master 2
1: High priority request to master 2
Reset to 0
0: Low priority request to master 3
1: High priority request to master 3
Reset to 0
0: Low priority request to master 4
1: High priority request to master 4
Reset to 0
0: Low priority request to master 5
1: High priority request to master 5
Reset to 0
0: Low priority request to master 6
1: High priority request to master 6
Reset to 0
0: Low priority request to master 7
1: High priority request to master 7
Reset to 0
0: Low priority request to master 8
1: High priority request to master 8
Reset to 0
Reset to 0
DESCRIPTION
April 2010, Revision 3.0
PCIe-to-PCI Reversible Bridge
PI7C9X110