PI7C9X110BNBE Pericom Semiconductor, PI7C9X110BNBE Datasheet - Page 95

IC PCIE TO PCI REV BRG 160LFBGA

PI7C9X110BNBE

Manufacturer Part Number
PI7C9X110BNBE
Description
IC PCIE TO PCI REV BRG 160LFBGA
Manufacturer
Pericom Semiconductor
Datasheets

Specifications of PI7C9X110BNBE

Applications
PCI-to-PCI Bridge
Interface
I²C
Voltage - Supply
1.8 V
Package / Case
160-LBGA
Mounting Type
Surface Mount
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Operating Temperature (max)
85C
Rad Hardened
No
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PI7C9X110BNBE
Manufacturer:
PLX
Quantity:
1 238
Part Number:
PI7C9X110BNBE
Manufacturer:
PERICOM31
Quantity:
193
Part Number:
PI7C9X110BNBE
Manufacturer:
Pericom
Quantity:
10 000
Part Number:
PI7C9X110BNBE
Manufacturer:
PERICOM
Quantity:
20 000
Part Number:
PI7C9X110BNBE
0
7.5.49 GPIO DATA AND CONTROL REGISTER – OFFSET 78h
7.5.50 SECONDARY INTERRUPT LINE REGISTER – OFFSET 7Ch
7.5.51 SECONDARY INTERRUPT PIN REGISTER – OFFSET 7Ch
7.5.52 SECONDARY MINIMUM GRANT REGISTER – OFFSET 7Ch
7.5.53 SECONDARY MAXIMUM LATENCY TIMER REGISTER – OFFSET 7Ch
Pericom Semiconductor – Confidential
BIT
9
10
11
BIT
15:12
19:16
23:20
27:24
31:28
BIT
7:0
BIT
15:8
BIT
23:16
BIT
FUNCTION
Secondary Master Timeout
Master Timeout Status
Discard Timer SERR_L
Enable
FUNCTION
GPIO Output Write-1-to-
Clear
GPIO Output Write-1-to-Set
GPIO Output Enable Write-
1-to-Clear
GPIO Output Enable Write-
1-to-Set
GPIO Input Data Register
FUNCTION
Secondary Interrupt Line
FUNCTION
Secondary Interrupt Pin
FUNCTION
Secondary Minimum Grant
FUNCTION
TYPE
TYPE
TYPE
TYPE
TYPE
TYPE
RWC
RW
RW
RW
RW
RW
RW
RW
RO
RO
RO
Page 95 of 144
DESCRIPTION
0: Secondary discard timer counts 215 PCI clock cycles
1: Secondary discard timer counts 210 PCI clock cycles
REVERSE BRIDGE – Bit is RO and ignored by PI7C9X110
Reset to 0
Bit is set when the discard timer expires and a delayed completion is
discarded at the PCI interface for the forward or reverse bridge
Reset to 0
Bit is set to enable to generate ERR_NONFATAL or ERR_FATAL for
forward bridge, or assert SERR_L for reverse bridge as a result of the
expiration of the discard timer.
Reset to 0
DESCRIPTION
Reset to 0h
Reset to 0h
Reset to 0h
Reset to 0h
Reset to 0h
DESCRIPTION
These bits apply to forward bridge only.
For initialization code to program to tell which input of the interrupt
controller the bridge’s INTA_L in connected to.
Reset to 00000000
DESCRIPTION
These bits apply to forward bridge only.
00000001: Designates interrupt pin INTA_L is used
Reset to 00h when reverse mode or 01h when forward mode.
DESCRIPTION
This register is valid only in forward bridge mode. It specifies how long of a
burst period that PI7C9X110 needs on the secondary bus in the units of ¼
microseconds.
Reset to 0
DESCRIPTION
April 2010, Revision 3.0
PCIe-to-PCI Reversible Bridge
PI7C9X110

Related parts for PI7C9X110BNBE