AM79C973BKC AMD (ADVANCED MICRO DEVICES), AM79C973BKC Datasheet
AM79C973BKC
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AM79C973BKC Summary of contents
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PRELIMINARY Am79C973/Am79C975 PCnet™-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY DISTINCTIVE CHARACTERISTICS Single-chip PCI-to-Wire Fast Ethernet controller — 32-bit glueless PCI host interface — Supports PCI clock frequency from MHz independent of network clock ...
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Look-Ahead Packet Processing (LAPP) data handling technique reduces system overhead by allowing protocol analysis to begin before the end of a receive frame Includes Programmable Inter Packet Gap (IPG) to address less network aggressive MAC controllers Offers the Modified Back-Off ...
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The Am79C973 and Am79C975 controllers’ advanced CMOS design allows the bus interface to be connected to either a +5 +3.3-V signaling environment. A compliant IEEE 1149.1 JTAG test interface for board- level testing ...
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BLOCK DIAGRAM EBUA_EBA[7:0] EBDA[15:8] EBD[7:0] EROMCS AS_EBOE EBWE EBCLK CLK RST AD[31:0] C/BE[3:0] PAR FRAME TRDY IRDY STOP IDSEL FIFO DEVSEL PCI Bus REQ Interface GNT Unit PERR SERR INTA FIFO Control Buffer Management Unit TCK JTAG TMS Port TDI ...
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TABLE OF CONTENTS DISTINCTIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Bus Acquisition ...
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Scrambler/Descrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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PCI Revision ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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CSR24: Base Address of Receive Ring Lower . . . . . . . . . . . . . . . . . . . . . . ...
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CSR114: Receive Collision Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 CSR116: ...
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ANR1: Status Register (Register 195 ANR2 ...
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Node ID Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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LIST OF FIGURES Figure 1. Slave Configuration Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figure 49. OnNow Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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LIST OF TABLES Table 1. Interrupt Flags ...
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Table 47. ANR6: Auto-Negotiation Expansion Register (Register 199 Table 48. ANR7: Auto-Negotiation Next Page Register (Register ...
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RELATED AMD PRODUCTS Part No. Description Controllers Am79C90 CMOS Local Area Network Controller for Ethernet (C-LANCE™) Integrated Controllers Am79C930 PCnet™-Mobile Single Chip Wireless LAN Media Access Controller Am79C940 Media Access Controller for Ethernet (MACE™) Am79C961A PCnet-ISA II Full Duplex Single-Chip ...
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CONNECTION DIAGRAM (PQR160) IDSEL 1 2 AD23 VSSB 3 AD22 4 5 VDD_PCI AD21 6 7 AD20 8 VDD 9 AD19 10 AD18 VSSB 11 12 AD17 13 VDD_PCI 14 AD16 15 C/BE2 VSS 16 17 FRAME 18 IRDY 19 ...
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CONNECTION DIAGRAM (PQL176 IDSEL 4 AD23 5 VSSB 6 AD22 7 VDD_PCI 8 AD21 9 AD20 10 VDD 11 AD19 12 AD18 13 VSSB 14 AD17 15 VDD_PCI 16 AD16 17 C/BE2 18 VSS 19 ...
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CONNECTION DIAGRAM (PQR160) - IDSEL 1 2 AD23 VSSB 3 4 AD22 VDD_PCI 5 6 AD21 AD20 7 8 VDD 9 AD19 10 AD18 11 VSSB 12 AD17 13 VDD_PCI 14 AD16 15 C/BE2 VSS 16 17 FRAME 18 IRDY ...
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CONNECTION DIAGRAM (PQL176 IDSEL 4 AD23 5 VSSB 6 AD22 7 VDD_PCI 8 AD21 9 AD20 10 VDD 11 AD19 12 AD18 13 VSSB 14 AD17 15 VDD_PCI 16 AD16 17 C/BE2 18 VSS ...
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PIN DESIGNATIONS (PQR160) (Am79C973/Am79C975) Listed By Pin Number Pin Pin Pin Pin No. Name No. Name 1 IDSEL 41 AD8 2 AD23 42 C/BE0 3 VSSB 43 VSSB 4 AD22 44 AD7 5 VDD_PCI 45 VDD_PCI 6 AD21 46 AD6 ...
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PIN DESIGNATIONS (PQL176) (Am79C973/Am79C975) Listed By Pin Number Pin Pin Pin Pin No. Name No. Name IDSEL 47 AD8 4 AD23 48 C/BE0 5 VSSB 49 VSSB 6 AD22 50 AD7 ...
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PIN DESIGNATIONS (PQR160, PQL176) Listed By Group Pin Name Pin Function PCI Bus Interface AD[31:0] Address/Data Bus C/BE[3:0] Bus Command/Byte Enable CLK Bus Clock DEVSEL Device Select FRAME Cycle Frame GNT Bus Grant IDSEL Initialization Device Select INTA Interrupt IRDY ...
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PIN DESIGNATIONS Listed By Group Pin Name Pin Function Physical Layer Interface (PHY) IREF Internal Current Reference RX± Serial Receive Data TX± Serial Transmit Data SDI± Signal Detect Input Power Management Interface RWU Remote Wake Up PME Power Management Event ...
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PIN DESIGNATIONS Listed by Group (Concluded) Pin Name Pin Function Power Supplies (MAC, PCI, Buffer, ROM) VDD Digital Power VSS Digital Ground VDDB I/O Buffer Power VSSB I/O Buffer Ground VDD_PCI PCI I/O Buffer Power 2 Power Supplies (PHY) DVDDA ...
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PIN DESIGNATIONS Listed By Driver Type The following table describes the various types of out- put drivers used in the Am79C973/Am79C975 control- ler. All I and I values shown in the table apply to 3 signaling. Name ...
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ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. AM79C973 AM79C975 K\V Valid Combinations AM79C973, AM79C975 ...
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PIN DESCRIPTIONS PCI Interface AD[31:0] Address and Data Address and data are multiplexed on the same bus inter- face pins. During the first clock of a transaction, AD[31:0] contain a physical address (32 bits). During the subse- quent clocks, AD[31:0] ...
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INTA Interrupt Request An attention signal which indicates that one or more of the following status flags is set: EXDINT, IDON, MERR, MISS, MFCO, MPINT, RCVCCO, RINT, SINT, TINT, TXSTRT, UINT, MCCINT, MPDTINT, MAPINT, MRE- INT, and STINT. Each status ...
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REQ Bus Request The Am79C973/Am79C975 controller asserts REQ pin as a signal that it wishes to become a bus master. REQ is driven high when the Am79C973/Am79C975 control- ler does not request the bus. In Power Management mode, the REQ ...
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BCR4). The LED0 pin polarity is programma- ble, but by default it is active LOW. When the LED0 pin polarity is programmed to active LOW, the output is an open drain driver. When the LED0 pin polarity is ...
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This pin is implemented for designs that do not support the PME function. Three bits that are loaded from the EEPROM into CSR116 can program the characteristics of this pin: 1. RWU_POL determines the polarity of the ...
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EBDA[15:8] Expansion Bus Data/Address [15:8] Output When EROMCS is asserted low, EBDA[15:8] contain address bits [15:8] for boot device accesses. The EBDA[15:8] signals are driven to a constant level to conserve power while no access on the Expansion Bus is ...
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TX_ER is unused and is reserved for future use and will always be driven to a logical zero. Note: The TX_ER pin is multiplexed with the EBUA_EBA7 pin. COL Collision COL is an input that indicates that a ...
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Start of Frame Delimiter is driven on RXD[3:0], and must remain asserted until after the rising edge of RX_CLK, when the last nibble of the CRC is driven on RXD[3:0]. RX_DV must then be deasserted prior to the RX_CLK rising ...
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RX+, RX- Serial Receive Data MLT-3/PECL These pins are the 10BASE-T/100BASE-X port differ- ential receiver pairs. They receive MLT-3 data and are connected ...
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MTX_DONEM) located in the Com- mand register. Note: The SMI interrupt acknowledge does not follow the SMBus alert protocol, but simply requires clearing the interrupt bit. Power Supply VDDB I/O Buffer Power (6 Pins) There are seven power supply ...
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BASIC FUNCTIONS System Bus Interface The Am79C973/Am79C975 controllers are designed to operate as a bus master during normal operations ave ...
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DETAILED FUNCTIONS Slave Bus Interface Unit The slave bus interface unit (BIU) controls all accesses to the PCI configuration space, the Control and Status Registers (CSR), the Bus Configuration Registers (BCR), the Address PROM (APROM) locations, and the Expansion ROM. ...
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Am79C973/Am79C975 controllers assert DEVSEL if it detects an address match and the access is a memory cycle. DEVSEL is asserted two clock cycles after the host has asserted FRAME. See Figure 1 and Figure 2. CLK ...
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CLK 1 2 FRAME AD ADDR C/BE 0010 PAR IRDY TRDY DEVSEL STOP Figure 3. Slave Read Using I/O Command CLK 1 2 FRAME ADDR AD 0111 C/BE PAR PAR IRDY TRDY DEVSEL STOP Figure 4. Slave Write Using Memory ...
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Expansion ROM Transfers The host must initialize the Expansion ROM Base Ad- dress register at offset 30H in the PCI configuration space with a valid address before enabling the access to the device. The Am79C973/Am79C975 controllers will not react to ...
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During the boot procedure, the system will try to find an Expansion ROM. A PCI system assumes that an Ex- pansion ROM is present when it reads the ROM signa- ture 55H (byte 0) and AAH (byte 1). Slave Cycle ...
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If the host is not yet ready when the Am79C973/ Am79C975 controller asserts TRDY, the device will wait for the host to assert IRDY. When the host asserts IRDY and FRAME is still asserted, the Am79C973/ Am79C975 controller will finish ...
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CLK 1 FRAME AD C/BE PAR PERR IRDY TRDY DEVSEL Figure 10. Slave Cycle Data Parity Error Response Master Bus Interface Unit The master Bus Interface Unit (BIU) controls the acqui- sition of the PCI bus and all accesses to ...
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AD[31:0] and C/BE[3:0] on clock 5. FRAME is asserted at clock 5 indicating a valid ad- dress and command on AD[31:0] and C/BE[3:0]. CLK FRAME AD C/BE IRDY REQ GNT Figure 11. Bus Acquisition In ...
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CLK 1 2 FRAME AD C/BE PAR IRDY TRDY DEVSEL REQ GNT DEVSEL is sampled CLK 1 FRAME AD C/BE PAR IRDY TRDY DEVSEL REQ GNT DEVSEL is sampled Figure 13. Burst Read Transfer (EXTREQ = 0, MEMCMD = 0) ...
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Basic Non-Burst Write Transfer By default, the Am79C973/Am79C975 controller uses non-burst cycles in all bus master write operations. All Am79C973/Am79C975 controller non-burst write ac- cesses are of the PCI command type Memory Write (type 7). The byte enable signals indicate ...
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Figure 15 shows a typical burst write access. The Am79C973/Am79C975 controller arbitrates for the bus, is granted access, and writes four 32-bit words (DWords) to the system memory and then releases the bus. In this example, the memory system extends ...
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CLK 1 2 FRAME AD C/BE PAR IRDY TRDY DEVSEL STOP REQ GNT DEVSEL is sampled Disconnect Without Data Transfer Figure 17 shows a target disconnect sequence during which no data is transferred. STOP is asserted on clock 4 without ...
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CLK 1 2 FRAME AD ADDR i C/BE 0111 PAR IRDY TRDY DEVSEL STOP REQ GNT DEVSEL is sampled Figure 17. Disconnect Without Data Transfer RTABORT (PCI Status register, bit 12) will be set to indicate that the Am79C973/Am79C975 controller ...
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CLK FRAME ADDR DATA AD 0111 0000 C/BE PAR PAR IRDY TRDY DEVSEL STOP REQ GNT DEVSEL is sampled Figure 18. Target Abort When the preemption occurs after the counter has counted down to 0, the ...
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CLK FRAME AD C/BE PAR IRDY TRDY DEVSEL REQ GNT Figure 19. Preemption During Non-Burst Transaction CLK FRAME AD C/BE PAR IRDY TRDY DEVSEL REQ GNT Figure 20. Preemption During Burst Transaction ...
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CLK FRAME AD ADDR 0111 C/BE PAR PAR IRDY TRDY DEVSEL REQ GNT DEVSEL is sampled Figure 21. Master Abort CLK ...
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Whenever the Am79C973/Am79C975 controller is the current bus master and a data parity error occurs, SINT (CSR5, bit 11) will be set to 1. When SINT is set, INTA is asserted if the enable bit SINTE (CSR5, bit 10) is ...
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CLK FRAME AD IADD i DATA 0110 0000 C/BE PAR PAR IRDY TRDY DEVSEL REQ GNT DEVSEL is sampled Figure 23. Initialization Block Read In ...
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Descriptor DMA Transfers Am79C973/Am79C975 microcode will determine when a descriptor access is required. A descriptor DMA read will consist of two data transfers. A descriptor DMA write will consist of one or two data transfers. The de- scriptor DMA transfers ...
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CLK FRAME AD MD1 DATA C/BE 0110 0000 PAR PAR IRDY TRDY DEVSEL REQ GNT DEVSEL is sampled Figure 25. Descriptor Ring Read In ...
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Table 6. Descriptor Write Sequence SWSTYLE BWRITE BCR20[7:0] BCR18[5] AD Bus Sequence Address = XXXX XX04h Data = MD2[15:0], MD1[15: Idle Address = XXXX XX00h Data = MD1[31:24] Address = XXXX XX08h Data = MD2[31: Idle ...
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CLK FRAME AD MD2 DATA C/BE 0111 0000 PAR PAR IRDY TRDY DEVSEL REQ GNT DEVSEL is sampled Figure 27. Descriptor Ring Write In Non-Burst ...
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Burst FIFO DMA Transfers Bursting is only perfor med by the Am79C973/ Am79C975 controller if the BREADE and/or BWRITE bits of BCR18 are set. These bits individually enable/ disable the ability of the Am79C973/Am79C975 con- troller to perform burst accesses ...
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CLK FRAME AD ADD DATA DATA C/BE 0111 0000 PAR PAR PAR IRDY TRDY DEVSEL REQ GNT DEVSEL is sampled Figure 30. FIFO Burst Write At End Of Unaligned Buffer The exact number of total transfer ...
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Re-initialization may be done via the initialization block or by setting the STOP bit in CSR0, followed by writing to CSR15, and then setting the START bit in CSR0. Note that this form of restart will not perform the same ...
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The descriptor ring base addresses must be aligned to an 8-byte boundary and a maximum of 128 ring entries is allowed when the ring length is set through the TLEN and RLEN fields of the initialization block. Each ring ...
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CSR2 IADR[31:16] Initialization Block MOD PADR[15:0] PADR[31:16] PADR[47:32] LADRF[15:0] LADRF[31:16] LADRF[47:32] LADRF[63:48] RDRA[15:0] RLE RDRA[23:16] RES TDRA[15:0] TDRA[23:16] TLE RES Note: The value of CSR2, bits 15-8, is used as the upper 8-bits for all memory addresses during bus mas- ...
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CSR2 IADR[31:16] Initialization Block TLE RES RLE RES PADR[31:0] PADR[47:32] RES LADRF[31:0] LADRF[63:32] RDRA[31:0] TDRA[31:0] If RXON is cleared to 0, the Am79C973/Am79C975 controller will never poll RDTE locations. In order to avoid missing frames, the system should have ...
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OWN bit of this descriptor, the Am79C973/ Am79C975 controller will again immediately request the bus in order to access the next TDTE location in the ring. If the OWN bit is set and the buffer length is 0, the ...
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If a poll operation has revealed that the current and the next RDTE belong to the Am79C973/Am79C975 con- troller, then additional poll accesses are not necessary. Future poll operations will not include RDTE accesses as long as the Am79C973/Am79C975 controller ...
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STVAL and restart. The timer value STVAL (BCR31, bits 15-0) is in- terpreted as an unsigned number with a resolution of 256 Time Base Clock periods. For instance, a value of 122 ...
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Destination Address Handling The first 6 bytes of information after SFD will be inter- preted as the destination address field. The MAC en- gine provides facilities for physical (unicast), logical (multicast), and broadcast address reception. Error Detection The MAC engine ...
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See ANSI/IEEE Std 802.3-1993 Edition, 4.2.3.2.1: Note possible for the PLS carrier sense indication to fail to be asserted during a collision on the media. If the deference process simply times the inter-Frame gap based on this indication, ...
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IPG shrinkage below 4 ms will rarely be en- countered on a correctly configured network, and since the fragment size will be larger than the 4 ms blinding window, the IPG counter will be reset by a worst ...
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FIFO to start a transmis- sion. Automatic Pad Generation Transmit frames can be automatically padded to extend them to 64 data bytes (excluding preamble). This al- lows the minimum frame size of 64 ...
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The transmit FIFO ensures this by guaranteeing that data contained within the FIFO will not be overwritten until at least 64 bytes (512 bits) of preamble ...
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CSR12 to CSR14). The byte ordering is such that the first byte received from the network (after the SFD) must match the least significant byte of CSR12 (PADR[7:0]), and the sixth byte received must match the most significant byte of ...
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The number of bytes to be stripped is calculated from the embedded length field (as defined in the ISO 8802- 3 (IEEE/ANSI 802.3) definition) contained in the frame. The length indicates the actual number of LLC data bytes contained in ...
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FCS errors Late collision Host related receive exception conditions include MISS, BUFF, and OFLO. These are described in the section, Buffer Management Unit. Loopback Operation Loopback is a mode of operation intended for system diagnostics. In this mode, the transmitter ...
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PHY Control Register (ANR0) bit 8 is set Auto- Negotiation is disabled. Full-Duplex Link Status LED Support The Am79C973/Am79C975 controller provides bits in each of the LED Status registers (BCR4, BCR5, BCR6, BCR7) to display the Full-Duplex ...
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PHY/MAC Interface The internal MII-compatible interface provides the data path connection between the 10/100 PHY and 10/100 Media Access Control (MAC). The interface is compat- ible with Clause 22 of the IEEE 802.3 standard specifi- cation. Transmit Process The transmit ...
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Internal MII-Compatible Interface TXD[3:0] & TX_ER 4B/5B Encoder 5 TX_EN /J/K/ Insertion /T/R/ Insertion 5 DISALIGN Scrambler 5 DISSCR PDX 5 Serializer PECL MLT-3 Conversion Conversion SDI TX Note: The 5-bit mode bypasses Encoder/Decoder ...
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Encoder The encoder converts the 4-bit nibble from the MII into five-bit code-groups, using a 4B/5B block coding scheme. The encoder operates on the 4-bit data nibble independent of the code-group boundar y. The 100BASE-X physical protocol data unit is ...
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Decoder The decoder performs the 5B/4B decoding of the re- ceived code-groups. The five bits of data are decoded into four bits of nibble data. The decoded nibble is then PCS Code-Group ...
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Scrambler/Descrambler The 4B/5B encoded data has repetitive patterns which result in peaks in the RF spectrum large enough to keep the system from meeting the standards set by regulatory agencies such as the FCC. The peaks in the radiated signal ...
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MLT-3 Figure 36. MLT-3 Waveform Serializer/Deserializer and Clock Recovery The Physical Data Transceiver (PDX CMOS all digital core that is used in the 10/100 PHY. It employs new circuit techniques to ...
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RX+ 49.9 50 49.9 50 RX– .01 µF SDI+ SDI– TX+ 49 TX– 3 0.1 F Notes: 1. The isolation transformers include common-mode chokes. 2. Consult magnetics vendors for appropriate termination schemes. ...
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Clock Data Clock Manchester Manchester Encoder Decoder Squelch Circuit TX Driver RX Driver TX RX Figure 38. 10BASE-T Transmit and Receive Data ...
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The Am79C973/Am79C975 device implements the transmit and receive Auto-Negotiation algorithm as de- fined in IEEE 802.3u, Section 28. The Auto-Negotiation algorithm uses a burst of link pulses called Fast Link Pulses (FLPs). The burst of link pulses are spaced be- ...
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EAR pin becomes active during the first 64 bytes of the frame (excluding preamble and SFD). This allows external address lookup logic approxi- mately 58 byte times after the last destination address bit is available to generate ...
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RX_DV to input the data into the receive frame tag reg- ister. At the deassertion of the RX_DV, the receive frame tag register will no longer accept data from the RX_CLK RX_DV SF/BD MIIRXFRTGE MIIRXFRTGD Expansion Bus Interface The Am79C973/Am79C975 ...
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ROM data are stored in holding registers. One clock cycle after the last data byte is available, the Am79C973/Am79C975 controller asserts TRDY. The access time for the Expansion ROM or the EB- DATA (BCR30) device (t ) during read ...
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Am79C975 controller will not react to any access to the Expansion ROM until both MEMEN (PCI Command reg- ister, bit 1) and ROMEN (PCI Expansion ROM Base Address register, bit 0) are set to 1. After the Expansion ROM is ...
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EBD[7:0] Am79C973 EBUA_EBA[7:0] EROMCS EBDA[15:8] AS_EBOE Figure 42. EPROM Only Configuration for the Expansion Bus (>64K EPROM) Since setting MEMEN also enables memory mapped access to the I/O resources, attention must be given to the PCI Memory Mapped I/O Base ...
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CLK EBUA_EBA [7:0] Latched Address EBDA [15:8] EBD AS_EBO EROMCS FRAME IRDY TRDY DEVSEL Figure 43. Expansion ROM Bus Read Sequence CLK EBUA_EBA[7:0] EBDA[15:8] EBD[7:0] EROMCS AS_EBOE Figure 44. Flash Read from Expansion Bus Data Port The EROMCS ...
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CLK EBUA_EBA[7:0] EBDA[15:8] EBD[7:0] EROMCS AS_EBOE EBWE Figure 45. Flash Write from Expansion Bus Data Port AMD Flash Programming AMD’s Flash products are programmed on a byte-by- byte basis. Programming is a four bus cycle operation. There are two “unlock” ...
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SRAM Configuration The Am79C973/Am79C975 controller supports inter- nal SRAM as a FIFO extension as well as providing a read/write data path to the SRAM. The Am79C973/ Am79C975 controller contains 12 Kbytes of SRAM. Internal SRAM Configuration The SRAM_SIZE (BCR25, bits ...
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PCI Bus Interface Unit Buffer Management Unit Figure 46. Block Diagram No SRAM Configuration PCI Bus Interface Unit Buffer Management Unit Figure 47. Block Diagram Low Latency Receive Configuration ...
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EEPROM Interface The Am79C973/Am79C975 controller contains a built- in capability for reading and writing to an external serial 93C46 EEPROM. This built-in capability consists of an interface for direct connection to a 93C46 compatible EEPROM, an automatic EEPROM read feature, ...
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BCR35 PCI Vendor ID BCR36 PCI Power Capabilities (PMC) Alias Regis- ter BCR37 PCI DATA Register Zero (DATA0) Alias Register BCR38 PCI DATA Register One (DATA1) Alias Register BCR39 PCI DATA Register Two (DATA2) Alias Register BCR40 PCI DATA (DATA3) ...
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Word Byte Address Addr. Most Significant Byte 2nd byte of the ISO 8802-3 (IEEE/ANSI 00h* 01h 802.3) station physical address for this node 01h 03h 4th byte of the node address 02h 05h 6th byte of the node address 03h ...
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Word Byte Most Significant Byte Addr. Addr. 2nd byte of the ISO 8802-3 (IEEE/ANSI 802.3) 00h* 01h station physical address for this node 01h 03h 4th byte of the node address 02h 05h 6th byte of the node address 03h ...
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The LED pins can be configured to operate in either open-drain mode (active low totem-pole mode (active high). The output can be stretched to allow the human eye to recognize even short events that last only several microseconds. ...
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Magic Packet MPPEN PG MPMODE MPEN Link Change LCMODE Link Change H_RESET Pattern Match BCR47 BCR46 Input Pattern Pattern Match RAM (PMR) OnNow Wake-Up Sequence The system software enables the PME pin by setting the PME_EN bit in the PMCSR ...
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LCDET bit is set, the RWU pin will be asserted and the PME_STATUS bit (PMCSR register, bit 15) will be set. If either the PME_EN bit (PMCSR, bit 8) or the PME_EN_OVR bit (CSR116, bit 10) are set, then ...
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BCR 47 BCR Bit Number PMR_B4 Pattern Match RAM Address pointer 1 P7 pointer 2 Data Byte 3 2+n Data Byte 4n+3 Date Byte 4n+2 J Data Byte 3 J+m Data Byte ...
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When the Am79C973/Am79C975 controller detects a Magic Packet frame, it sets the MPMAT bit (CSR116 ...
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There are four possible operation modes in the BSR cell shown in Table 17. Table 17. BSR Mode Of Operation 1 Capture 2 Shift 3 Update 4 System Function Other Data Registers Other data registers are the following: 1. Bypass ...
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STOP terminates all network activity abruptly. The host can use the suspend mode (SPND, CSR5, bit 0) to ter- minate all network activity in an orderly sequence be- fore setting the STOP bit. Power on Reset Power on Reset (POR) ...
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I/O Resources The Am79C973/Am79C975 controller requires 32 bytes of address space for access to all the various internal registers as well as to some setup information stored in an external serial EEPROM. A software reset port is available, too. The ...
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All I/O resources must be accessed in word quantities and on word addresses. The Address PROM locations can also be read in byte quantities. The only allowed DWord operation is a write access to the RDP, which switches the device ...
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Table 21. Legal I/O Accesses in Word I/O Mode (DWIO = 0) AD[4:0] BE[3:0] Type 0XX00 1110 RD 0XX01 1101 RD 0XX10 1011 RD 0XX11 0111 RD 0XX00 1100 RD 0XX10 0011 RD 10000 1100 RD 10010 0011 RD 10100 ...
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USER ACCESSIBLE REGISTERS The Am79C973/Am79C975 controller has four types of user registers: the PCI configuration registers, the Con- trol and Status registers (CSR), the Bus Control regis- ters (BCR), and the PHY Management registers (ANR). The Am79C973/Am79C975 controller implements all ...
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CSR82 Bus Activity Timer CSR100 Memory Error Timeout CSR116^ OnNow Miscellaneous CSR122 Receiver Packet Alignment Control CSR125^ MAC Enhanced Configuration Control BCR2^ Miscellaneous Configuration BCR4^ LED0 Status BCR5^ LED1 Status BCR6^ LED2 Status BCR7^ LED3 Status BCR9^ Full-Duplex Control BCR18^ ...
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AMD’s product line. The Am79C973/ Am79C975 Device ID is 2000h. Note that this Device ID is not the same as the Part number in CSR88 and CSR89. The Device ID is assigned by AMD. The De- vice ID ...
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For memory mapped I/O, the host must program the PCI Mem- ory Mapped I/O Base Address register with a valid memory ad- dress before setting MEMEN. For accesses to the Expansion ROM, the host must program the PCI Expansion ROM ...
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RMABORT Am79C973/Am79C975 controller and cleared by writing a 1. Writ- ing a 0 has no effect. RMABORT is cleared by H_RESET and is not affected by S_RESET or by setting the STOP bit. 12 RTABORT Received Target ABORT is set ...
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The value of this register is 00h. The PCI Programming Interface register is located at offset 09h in the PCI Configuration Space read only. PCI Sub-Class Register Offset 0Ah The ...
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DEVSEL indicating it will respond to the access. IOBASE is read and written by the host. IOBASE is cleared by H_RESET and is not affected by S_RESET or by setting the STOP bit. 4-2 IOSIZE I/O size requirements. ...
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PCI Subsystem Vendor ID Register Offset 2Ch The PCI Subsystem Vendor ID register is a 16-bit reg- ister that together with the PCI Subsystem ID uniquely identifies the add-in card or subsystem the Am79C973/ Am79C975 controller is used in. Subsystem ...
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PCI Capabilities Pointer Register Offset 34h Bit Name Description 7-0 CAP_PTR The PCI Capabilities pointer Register is an 8-bit register that points to a linked list of capabili- ties implemented on this device. This register has a default value of ...
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PCI Power Management Capabilities Register (PMC) Offset 42h Note: All bits of this register are loaded from EEPROM. The register is aliased to BCR36 for testing purposes. Bit Name Description 15-11 PME_SPT PME Support. This 5-bit field indi- cates the ...
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Read/write accessible always. Sticky bit. This bit is reset by POR. H_RESET, S_RESET, or setting the STOP bit has no ef- fect. 14-13 DATA_SCALE Data Scale. This two bit read- only field indicates the scaling factor to be used when ...
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Then a second access is performed, this time to the RDP offset of 10h (for either WIO or DWIO mode). The RDP access is a read access, and since RAP has just been loaded with the value of ...
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MISSM (CSR3, bit 12 MISS assertion will set the ERR bit, regardless of the settings of IENA and MISSM. Read/Write accessible always. MISS is cleared by the host by writing a 1. Writing a 0 has no ...
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SLPINT, INTA will be active in- dependent of the state of INEA. Read accessible always. INTR is read only. INTR is cleared by clearing all of the active individual interrupt bits that have not been masked out. 6 IENA ...
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INIT clears the STOP bit. If STRT and INIT are set together, the Am79C973/Am79C975 controller initialization will be performed first. INIT is not cleared when the initialization sequence has com- pleted. Read/Write accessible always. INIT is set by writing a ...
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Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-13 RES Reserved locations. Read and written as zero. 12 MISSM Missed Frame Mask. If MISSM is set, the MISS bit will be masked and unable ...
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STP = 1, then some descriptors/ buffers may be skipped in the ring. While performing the search ...
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Byte swap only affects data transfers that involve the FIFOs. Initialization block transfers are not affected by the setting of the BSWP bit. Descriptor transfers are not affected by the setting of the BSWP bit. RDP, RAP, BDP and PCI ...
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MFCO Missed Frame Counter Overflow is set by Am79C975 controller when the Missed Frame Counter (CSR112 and CSR113) around. When MFCO is set, INTA is as- serted if IENA is 1 and the mask bit MFCOM is 0. Read/Write ...
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CSR5 and write back the value just read to clear the interrupt condition. Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15 TOKINTD Transmit OK Interrupt Disable. If ...
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Read/Write accessible always. EXDINTE is H_RESET and is not affected by S_RESET or setting the STOP bit. 5 MPPLBA Magic Packet Physical Logical Broadcast Accept. If MPPLBA is at its default value of 0, the Am79C973/Am79C975 controller will only detect ...
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In suspend mode, all of the CSR and BCR registers are accessi- ble. As long as the Am79C973/ Am79C975 controller is not reset while in suspend mode (by H_RESET, S_RESET or by set- ting the STOP bit), no re-initial- ization ...
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Am79C973/Am79C975 controller will completely receive a receive packet if it had already begun. Additionally, all transmit packets stored in the transmit FIFOs and the transmit buffer area in the SRAM (if one is en- abled) will be transmitted ...
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STINTE Software Timer Interrupt Enable. If STINTE is set, the STINT bit will be able to set the INTR bit. Read/Write accessible always. STINTE is set H_RESET and is not affected by S_RESET or setting the ...
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MAPINT (CSR7, bit 6) interrupt or the MCCIINTE is set to 1. Read/Write accessible always. MCCINTE is H_RESET and is not affected by S_RESET or setting the STOP bit. 3 MCCIINT PHY Management Command Complete Internal Interrupt. The ...
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Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR10: Logical Address Filter 2 Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as ...
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RES Reserved locations. Written as zeros and read as undefined. 15-0 PADR[47:32]Physical Address PADR[47:32].The this register are loaded from EE- PROM after H_RESET EEPROM (PRGAD, BCR19, bit 14). If the EEPROM is not present, the con- ...
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FCOLL to be valid. If FCOLL = 1, a collision will be forced during loopback transmis- sion attempts, which will result in a Retry Error. If FCOLL = 0, the Force Collision ...
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CSR17: Initialization Block Address Upper Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 IADRH This register is an alias of CSR2. Read/Write accessible only when either the STOP or the SPND bit is ...
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Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR24: Base Address of Receive Ring Lower Bit Name Description 31-16 RES Reserved locations. Written as zeros and ...
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H_RESET, S_RESET, or STOP. CSR31: Base Address of Transmit Ring Upper Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 BADXU Contains the upper 16 bits of the base address of the Transmit ...
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H_RESET, S_RESET, or STOP. CSR38: Next Next Transmit Descriptor Address Lower Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 NNXDAL Contains the lower 16 bits of the next next transmit descriptor ad- ...
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RES Reserved locations. Written as zeros and read as undefined. 15-12 RES Reserved locations. Read and written as zeros. 11-0 NRBC Next Receive Byte Count. This field is a copy of the BCNT field of RMD1 of the next ...
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H_RESET, S_RESET, or STOP. CSR48: Receive Poll Time Counter Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 RXPOLL Receive Poll Time Counter. This counter is incremented by the Am79C973/Am79C975 controller microcode and ...
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Am79C975 controller to use 32- bit software structures. APERREN does not affect the re- porting of address parity errors or data parity errors that occur when the Am79C973/Am79C975 con- troller is the target of the transfer. Read anytime, write accessible ...
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CSR60: Previous Transmit Descriptor Address Lower Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. SWSTYLE Style [7:0] Name LANCE/ 00h PCnet-ISA controller 01h RES PCnet-PCI 02h controller PCnet-PCI 03h controller All Other Reserved P ...
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CSR61: Previous Transmit Descriptor Address Upper Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 PXDAU Contains the upper 16 bits of the previous transmit descriptor ad- dress pointer. The Am79C973/ Am79C975 controller has ...
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CSR67: Next Transmit Status Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 NXST Next Transmit Status. This field is a copy of bits 31-16 of TMD1 of the next transmit descriptor. Read/Write accessible ...
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H_RESET, S_RESET, or STOP. CSR80: DMA Transfer Counter and FIFO Threshold Control Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-14 RES Reserved locations. Written as zeros and read as undefined. 13-12 RCVFW[1:0] ...
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Note that when the SRAM is be- ing used, if the NOUFLO bit (CSR80, bit 14) is set to 1, there is the additional restriction that the complete transmit ...
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CSR82: Transmit Descriptor Address Pointer Lower Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 TXDAPL Contains the lower 16 bits of the transmit descriptor address cor- responding to the last buffer of the ...
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VER is read only. Write opera- tions are ignored. 27-12 PARTID Part number. The 16-bit code for the Am79C973 0010 0110 0010 0101 (2625h) and the code for the Am79C975 is 0010 0110 0010 0111 (2627h). This register is exactly ...
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MERRM bit (CSR3, bit 11) and the IENA bit (CSR0, bit 6). The value in this register is inter- preted as the unsigned number of bus clock periods divided by two, (i.e., the value in this register ...
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PME_EN_OVR PME_EN Overwrite. When this bit is set and the MPMAT or LCDET bit is set, the PME pin will always be asserted regardless of the state of PME_EN bit. Read/Write accessible only when either the STOP bit or ...
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Cleared by H_RESET and is not affected by S_RESET or setting the STOP bit. 1 RWU_POL RWU Pin Polarity. If RWU_POL is set to 1, the RWU pin is normal- ly HIGH and asserts LOW; other- wise ...
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By pro- gramming a larger number of bit times, the Am79C975 MAC will become less aggressive on the network and may defer more often than normal. The performance of the Am79C973/Am79C975 controller may decrease as the ...
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BCR0: Master Mode Read Active Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 MSRDA Reserved H_RESET, the value in this regis- ter will be 0005h. The setting of this register has no effect ...
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RAP Mnemonic Default 0 MSRDA 0005h 1 MSWRA 0005h 2 MC 0002h 3 Reserved N/A 4 LED0 00C0h 5 LED1 0084h 6 LED2 0088h 7 LED3 0090h 8 Reserved N/A 9 FDC 0000h 10-15 Reserved N/A 16 IOBASEL N/A 17 ...
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Reserved 0000h 54 Reserved 0000h Note: *Program only as ‘0’ value. 160 Table 29. BCR Registers (Am79C973) Reserved (for Am79C975) Reserved (for Am79C975) Am79C973/Am79C975 Yes* Yes* Yes* Yes* ...
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RAP Mnemonic Default 0 MSRDA 0005h 1 MSWRA 0005h 2 MC 0002h 3 Reserved N/A 4 LED0 00C0h 5 LED1 0084h 6 LED2 0088h 7 LED3 0090h 8 Reserved N/A 9 FDC 0000h 10-15 Reserved N/A 16 IOBASEL N/A 17 ...
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M_IP_ADR[15:0] 0000h 54 M_IPADR[31:16] 0000h BCR2: Miscellaneous Configuration Note: Bits 15-0 in this register are programmable through the EEPROM. Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15 SMIUEN (For Am79C975 only) SMIUEN ...
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D5 bit position (see Appendix B on SMIU Bus Fre- quency. Read/Write accessible always. I2C_M2 is cleared by H_RESET and is unaffected by S_RESET or by setting the STOP bit. 8 APROMWE Address PROM Write Enable. The ...
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See the section on External Ad- dress Detection for more details. Read/Write accessible always. EADISEL is H_RESET and is unaffected by S_RESET or by setting the STOP bit. 2 SLEEP_SFEX Setting this bit will reduce the power consumption of the ...
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LEDDIS LED Disable. This bit is used to disable the LED output. When LEDDIS has the value 1, then the LED output will always be dis- abled. When LEDDIS has the val then the LED output value ...
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Read/Write accessible always. RCVE is cleared by H_RESET and is not affected by S_RESET or setting the STOP bit. 1 RES Reserved location. Written and read as zeros. 0 COLE ...
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RES Reserved locations. Written and read as zeros. 9 MPSE Magic Packet Status Enable. When this bit is set value passed to the LEDOUT bit in this register when Magic Packet mode is ...
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BCR6: LED2 Status BCR6 controls the function(s) that the LED2 pin dis- plays. Multiple functions can be simultaneously enabled on this LED pin. The LED display will indicate the logical OR of the enabled functions. Note: When LEDPE (BCR2, bit ...
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Am79C975 controller is function- ing in a Link Pass state and full- duplex operation is enabled. When the Am79C975 controller is not func- tioning in a Link Pass state with full-duplex operation being en- abled, a value ...
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The logical value of the LEDOUT status signal is determined by the settings of the individual Status Enable bits of the LED register (bits 8 and 6-0). Read accessible always. This bit is read only; writes have no ef- fect. ...
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LNKSE Link Status Enable. When this bit is set, a value of 1 will be passed to the LEDOUT bit in this register in Link Pass state. Read/Write accessible always. LNKSE is cleared by H_RESET and is not affected ...
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When FDEN is set, the Am79C973/Am79C975 con- troller will operate in full-duplex mode. Do not set this bit when Auto-Negotiation is enabled. Read/Write accessible always. FDEN is reset H_RESET, ...
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The access time for the Expan- sion ROM or for the EBDATA (BCR30) device (t write operations can be calculat subtracting the clock to out- put delay for the EBUA EBA[7:0] outputs (t v_A_D the input to clock ...
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GNT at the beginning of the burst transaction. If EXTREQ is set to 1, REQ stays asserted until the last but one data phase of the burst transaction is done. This mode is useful for systems that implement an arbitration ...
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S_RESET or STOP. 4-3 PHYSEL[1:0] PHYSEL[1:0] bits allow for soft- ware controlled selection of differ- ent operation and test modes. The normal mode of operation is when both bits 0 and 1 are set to ...
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EEPROM after H_RESET, as well as to host-initiated PREAD commands. 14 PREAD EEPROM Read command bit. When this bit is set the host, the PVALID bit (BCR19, bit 15) will immediately be reset ...
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EESK/LED1/SFBD pin at the end of H_RESET. This value indi- cates whether or not an EE- PROM is present at the EEPROM interface. If this bit indi- cates that present. If this bit ...
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EEN = 1, then setup and hold times of the EEDI pin value with respect to the EESK signal edge are not guaranteed. ESK has no effect on the EESK pin unless the PREAD bit is set to 0 ...
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Am79C975 controller. This action is required, since the 16-bit soft- ware structures specified by the SSIZE32 = 0 setting will yield only 24 bits of address ...
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Read accessible always; write accessible only when either the STOP or the SPND bit is set. MAX_LAT is set to the value of FFh by H_RESET which results in a default maximum latency of 63.75 microseconds recom- mended ...
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RES Reserved locations. Written as zeros and read as undefined. 7-0 SRAM_SIZE SRAM Size. Specifies the upper 8 bits of the 16-bit total size of the SRAM buffer. SRAM_SIZE accounts for a 512- byte page. The starting address for ...
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LOLATRX Low Latency Receive. When the LOLATRX bit is set to 1, the Am79C973/Am79C975 controller will switch to an architecture ap- plicable to cut-through switches. The Am79C973/Am79C975 con- troller will assert a receive frame DMA after only 16 bytes ...
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Expansion Bus clock data, corruption will re- sult. CAUTION: The Clock will not support 100 Mbit operation and should only be selected in 10 Mbit only config- urations. CAUTION: The ...
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EBADDRL reaches FFFFh and LAAINC is set to 1, the Expansion Port Lower Address (EPADDRL) will roll over to 0000h. When the LAAINC bit is set to 0, the Expan- sion Port Lower Address will not be affected in any ...
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The STVAL value is interpreted as an unsigned number with a resolution of 256 Time Base Clock periods. For instance, a value of 122 ms would be pro- grammed with a value of 9531 (253Bh) if the Time Base Clock ...
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Read/Write accessible always. APEP is set H_RESET and is unaffected by S_RESET and the STOP bit. 10-8 APDW Auto-Poll Dwell Time. APDW de- termines the dwell time between PHY Management accesses when turned on. See Table 38. Table 38. APDW ...
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TXD[3:0] nibble data path is looped back onto the RXD[3:0] nibble data path. TX_CLK is looped back as RX_CLK. TX_EN is looped back as RX_DV. CRS is correctly OR’d with TX_EN and RX_DV and always encompass- es the transmit frame. ...
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Am79C973/Am79C975 ler. AMD’s Vendor ID is 1022h. Note that this Vendor ID is not the same as the Manufacturer ID in CSR88 and CSR89. The Vendor ID is assigned by the PCI Special Interest Group. ...
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Read accessible D1_SCALE is read only. Cleared by H_RESET and is not affected by S_RESET or setting the STOP bit. 7-0 DATA1 These bits correspond to the PCI DATA register (offset Register 47 of the PCI configuration space, bits 7-0). ...
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RES Reserved locations. Written as zeros and read as undefined. 9-8 D4_SCALE These bits correspond to the DATA_SCALE field of the PMC- SR (offset register 44 of the PCI configuration space, bits 14-13). Refer to the DATA_SCALE for the ...
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BCR44: PCI DATA Register Seven (DATA7) Alias Register Note: This register is an alias of the DATA register and also of the DATA_SCALE field of the PCMCR register. Since these two are read only, BCR44 provides a means of programming ...
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PMR word to be accessed. Following the write to BCR45, the PMR word may be read by reading BCR45, BCR46 and BCR47 in any order. To write to PMR word, the write to BCR45 must be followed ...
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Table 39. Am79C973/Am79C975 Internal PHY Management Register Set Register Address (in Decimal) Register Name 0 PHY Control 1 PHY Status 2-3 PHY Identifier Auto-Negotiation 4 Advertisement Auto-Negotiation Link 5 Partner Ability Auto-Negotiation 6 Expansion Auto-Negotiation Next 7 Page 8-15 Reserved ...
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Table 40. ANR0: PHY Control Register (Register 0) Reg Bits Name 0 15 Soft Reset (Note 2) Loopback 0 14 Speed Selection 0 13 (Note 3) Auto-Negotiation 0 12 Enable 0 11 Power Down Isolate 0 10 Restart Auto- 0 ...
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ANR1: Status Register (Register 1) The Status Register identifies the physical and Auto- negotiation capabilities of the local PHY. This register is read only; a write will have no effect. Table 41. ANR1: PHY Status Register (Register 1) Reg Bits ...
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ANR2 and ANR3: PHY Identifier (Registers 2 and 3) Registers 2 and 3 contain a unique PHY identifier, con- sisting of 22 bits of the organizationally unique IEEE Identifier, a 6-bit manufacturer’s model number, and a 4-bit manufacturer’s revision number. ...
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ANR4: Auto-Negotiation Advertisement Register (Register 4) This register contains the advertised ability of the Am79C973/Am79C975 device. The purpose of this Table 44. ANR4: Auto-Negotiation Advertisement Register (Register 4) Bit(s) Name When set, the device wishes to engage in next page ...
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ANR5: Auto-Negotiation Link Partner Ability Register (Register 5) The Auto-Negotiation Link Partner Ability Register is Read Only. The register contains the advertised ability Table 45. ANR5: Auto-Negotiation Link Partner Ability Register (Register 5) - Base Page Format Bit(s) Name 15 ...
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ANR6: Auto-Negotiation Expansion Register (Register 6) The Auto-Negotiation Expansion Register provides ad- ditional information which aids the Auto-Negotiation Table 47. ANR6: Auto-Negotiation Expansion Register (Register 6) Bit(s) Name 15:5 Reserved 1=Parallel detection fault Parallel Detection 4 Fault 0=No parallel detection ...
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ANR16: INTERRUPT Status and Enable Register (Register 16) The Interrupt bits indicate when there is a change in the Link Status, Duplex Mode, Auto-Negotiation status, or Speed status. Register 16 contains the interrupt status and interrupt enable bits. The status ...