AM79C973BKC AMD (ADVANCED MICRO DEVICES), AM79C973BKC Datasheet - Page 183

• Manufacturer Part Number: AM79C973BKC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKC

• Lead Free Status / Rohs Status: Not Compliant

2-0
BCR28: Expansion Bus Port Address Lower (Used
for Flash/EPROM and SRAM Accesses)
Bit
31-16 RES
15-0
CLK_FAC
1XX
000
001
010
011
CLK_FAC
EPADDRL
Name
Table 36. CLK_FAC Values
Clock Factor. These bits are used
to select whether the clock select-
ed by EBCS is used directly or if it
is divided down to give a slower
clock for running the Expansion
Bus access cycles. The possible
factors are given in Table 36.
Reserved locations. Written as
zeros and read as undefined.
Expansion Port Address Lower.
This address is used to provide
addresses for the Flash and
SRAM port accesses.
that can occur while it is being
used for the Expansion Bus
clock data, corruption will re-
sult.
CAUTION:
Clock will not support 100 Mbit
operation and should only be
selected in 10 Mbit only config-
urations.
CAUTION: The external clock
source
EBCLK pin must be a continu-
ous clock source at all times.
Read accessible always; write
accessible only when the STOP
bit is set. CLK_FAC is set to 000b
during H_RESET and is unaffect-
ed by S_RESET or STOP.
SRAM accesses are started
when a read or write is performed
on BCR30 and the FLASH (BCR
29, bit 15) is set to 0. During
SRAM accesses only bits in the
EPADDRL are valid. Since all
SRAM accesses are word orient-
Description
1/2 (divide by 2)
1/4 (divide by 4)
Clock Factor
Reserved
Reserved
used
1
The
to
Time
P R E L I M I N A R Y
drive
Am79C973/Am79C975
Base
the
BCR29: Expansion Port Address Upper (Used for
Flash/EPROM Accesses)
Bit
31-16 RES
15
14
FLASH
LAAINC
Name
Lower Address Auto Increment.
ed only, EPADDRL[0] is the least
significant word address bit. On
any byte write accesses to the
SRAM, the user will have to fol-
low
scheme. On any byte read ac-
cesses to the SRAM, the user will
have to chose which byte is
needed from the complete word
returned in BCR30.
Flash accesses are started when
a read or write is performed on
BCR30 and the FLASH (BCR 29,
bit 15) is set to 1. During Flash
accesses all bits in EPADDR are
valid.
Read accessible always; write
accessible only when the STOP
is set or when SRAM SIZE
(BCR25, bits 7-0) is 0. EPADDRL
is undefined after H_RESET and
is unaffected by S_RESET or
STOP.
Reserved locations. Written as
zeros and read as undefined.
Flash Access. When the FLASH
bit is set to 1, the Expansion Bus
access will be a Flash cycle.
When FLASH is set to 0, the Ex-
pansion Bus access will be a
SRAM cycle. For a complete de-
scription, see the section on Ex-
pansion Bus Accesses. This bit is
only applicable to reads or writes
to EBDATA (BCR30). It does not
affect Expansion ROM accesses
from the PCI system bus.
Read accessible always; write
accessible only when the STOP
bit is set. FLASH is 0 after
H_RESET and is unaffected by
S_RESET or the STOP bit.
When the LAAINC bit is set to 1,
the Expansion Port Lower Ad-
dress will automatically increment
by one after a read or write ac-
cess to EBDATA (BCR30). When
Description
the
read-modify-write
183