AM79C973BKC AMD (ADVANCED MICRO DEVICES), AM79C973BKC Datasheet - Page 126

• Manufacturer Part Number: AM79C973BKC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKC

• Lead Free Status / Rohs Status: Not Compliant

CSR1: Initialization Block Address 0
Bit
31-16
15-0
CSR2: Initialization Block Address 1
Bit
31-16
15-8
126
Name
RES
IADR[15:0] Lower 16 bits of the address of
Name
RES
IADR[31:24] If SSIZE32 is set (BCR20, bit 8),
INIT clears the STOP bit. If STRT
and INIT are set together, the
Am79C973/Am79C975 controller
initialization will be performed
first. INIT is not cleared when the
initialization sequence has com-
pleted.
Read/Write accessible always.
INIT is set by writing a 1. Writing
a 0 has no effect. INIT is cleared
by H_RESET, S_RESET, or by
setting the STOP bit.
zeros and read as undefined.
the Initialization Block. Bit loca-
tions 1 and 0 must both be 0 to
align the initialization block to a
DWord boundary.
This register is aliased with
CSR16.
Read/Write accessible only when
either the STOP or the SPND bit
is set. Unaffected by H_RESET
or S_RESET, or by setting the
STOP bit.
zeros and read as undefined.
then the IADR[31:24] bits will be
used strictly as the upper 8 bits of
the initialization block address.
However, if SSIZE32 is reset
(BCR20,
IADR[31:24] bits will be used to
generate the upper 8 bits of all
bus mastering addresses, as re-
quired for a 32-bit address bus.
Note that the 16-bit software
structures
SSIZE32 = 0 setting will yield
only 24 bits of address for the
Am79C973/Am79C975 bus mas-
Description
Reserved locations. Written as
Description
Reserved locations. Written as
bit
specified
8),
P R E L I M I N A R Y
then
Am79C973/Am79C975
by
the
the
7-0
CSR3: Interrupt Masks and Deferral Control
IADR[23:16] Bits 23 through 16 of the address
ter accesses, while the 32-bit
hardware
Am79C973/Am79C975 controller
is intended will require 32 bits of
address. Therefore, whenever
SSIZE32 = 0, the IADR[31:24]
bits will be appended to the 24-bit
initialization address, to each 24-
bit descriptor base address and
to each beginning 24-bit buffer
address in order to form complete
32-bit addresses. The upper 8
bits that exist in the descriptor ad-
dress registers and the buffer ad-
dress registers which are stored
on
Am79C975 controller will be
overwritten with the IADR[31:24]
value, so that CSR accesses to
these registers will show the 32-
bit address that includes the ap-
pended field.
If SSIZE32 = 1, then software will
provide 32-bit pointer values for
all of the shared software struc-
tures - i.e., descriptor bases and
buffer addresses, and therefore,
IADR[31:24] will not be written to
the upper 8 bits of any of these
resources, but it will be used as
the upper 8 bits of the initializa-
tion address.
This register is aliased with
CSR17.
Read/Write accessible only when
either the STOP or the SPND bit
is set. Unaffected by H_RESET,
S_RESET, or by setting the
STOP bit.
Read/Write accessible only when
either the STOP or the SPND bit
is set. Unaffected by H_RESET,
S_RESET, or by setting the
STOP bit.
of the Initialization Block. When-
ever this register is written,
CSR17 is updated with CSR2’s
contents.
board
for
the
which
Am79C973/
the