AM79C973BKC AMD (ADVANCED MICRO DEVICES), AM79C973BKC Datasheet - Page 174

• Manufacturer Part Number: AM79C973BKC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKC

• Lead Free Status / Rohs Status: Not Compliant

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174
DWIO
GNT at the beginning of the burst
transaction. If EXTREQ is set to
1, REQ stays asserted until the
last but one data phase of the
burst transaction is done. This
mode is useful for systems that
implement an arbitration scheme
without preemption and require
that REQ stays asserted through-
out the transaction.
Double Word I/O. When set, this
bit indicates that the Am79C973/
Am79C975 controller is pro-
grammed for DWord I/O (DWIO)
mode. When cleared, this bit indi-
cates
Am79C975 controller is pro-
grammed for Word I/O (WIO)
mode. This bit affects the I/O Re-
source Offset map and it affects
the
Am79C973/Am79C975
lers I/O resources. See the DWIO
and WIO sections for more de-
tails.
EXTREQ should not be set to 1
when the Am79C973/Am79C975
controller is used in a PCI bus ap-
plication.
Read accessible always, write
accessible only when either the
STOP or the SPND bit is set. EX-
TREQ is cleared by H_RESET
and is not affected by S_RESET
or STOP.
The initial value of the DWIO bit is
determined by the programming
of the EEPROM.
The value of DWIO can be al-
tered
Am79C973/Am79C975 control-
ler. Specifically, the Am79C973/
Am79C975 controller will set
DWIO if it detects a DWord write
access to offset 10h from the
Am79C973/Am79C975 controller
I/O base address (corresponding
to the RDP resource).
Once the DWIO bit has been set
to a 1, only a H_RESET or an EE-
PROM read can reset it to a 0.
(Note that the EEPROM read op-
eration will only set DWIO to a 0 if
defined
that
automatically
the
width
Am79C973/
P R E L I M I N A R Y
Am79C973/Am79C975
by
of
control-
the
the
6
5
BREADE
BWRITE
the appropriate bit inside of the
EEPROM is set to 0.)
Read accessible always. DWIO
is read only, write operations
have no effect. DWIO is cleared
by H_RESET and is not affected
S_RESET or by setting the STOP
bit.
Burst Read Enable. When set,
this bit enables burst mode during
memory read accesses. When
cleared, this bit prevents the de-
vice from performing bursting
during
Am79C973/Am79C975 controller
can perform burst transfers when
reading the initialization block,
the descriptor ring entries (when
SWSTYLE = 3) and the buffer
memory.
BREADE should be set to 1 when
the Am79C973/Am79C975 con-
troller is used in a PCI bus appli-
cation to guarantee maximum
performance.
Read accessible always; write
accessible only when either the
STOP or the SPND bit is set.
BREADE is cleared by H_RESET
and is not affected by S_RESET
or STOP.
Burst Write Enable. When set,
this bit enables burst mode during
memory write accesses. When
cleared, this bit prevents the de-
vice from performing bursting
during
Am79C973/Am79C975 controller
can perform burst transfers when
writing the descriptor ring entries
(when SWSTYLE = 3) and the
buffer memory.
BWRITE should be set to 1 when
the Am79C973/Am79C975 con-
troller is used in a PCI bus appli-
cation to guarantee maximum
performance.
Read accessible always, write
accessible only when either the
STOP or the SPND bit is set.
BWRITE is cleared by H_RESET
write
read
accesses.
accesses.
The
The