AM79C973BKC AMD (ADVANCED MICRO DEVICES), AM79C973BKC Datasheet - Page 40

• Manufacturer Part Number: AM79C973BKC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKC

• Lead Free Status / Rohs Status: Not Compliant

DETAILED FUNCTIONS
Slave Bus Interface Unit
The slave bus interface unit (BIU) controls all accesses
to the PCI configuration space, the Control and Status
Registers (CSR), the Bus Configuration Registers
(BCR), the Address PROM (APROM) locations, and
the Expansion ROM. Table 3 shows the response of
the Am79C973/Am79C975 controllers to each of the
PCI commands in slave mode.
Slave Configuration Transfers
The host can access the Am79C973/Am79C975 PCI
configuration space with a configuration read or write
command. The Am79C973/Am79C975 controllers will
assert DEVSEL during the address phase when IDSEL
is asserted, AD[1:0] are both 0, and the access is a
40
C[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Special Cycle
Memory Read
Command
Interrupt
Acknowledge
I/O Read
I/O Write
Reserved
Reserved
Memory Write
Reserved
Reserved
Configuration
Read
Configuration
Write
Memory Read
Multiple
Dual Address
Cycle
Memory Read
Line
Memory Write
Invalidate
Table 3. Slave Commands
Use
Not used
Not used
Read of CSR, BCR, APROM,
and Reset registers
Write to CSR, BCR, and
APROM
Memory mapped I/O read of
CSR, BCR, APROM, and
Reset registers
Read of the Expansion Bus
Memory mapped I/O write of
CSR, BCR, and APROM
Read of the Configuration
Space
Write to the Configuration
Space
Aliased to Memory Read
Not used
Aliased to Memory Read
Aliased to Memory Write
P R E L I M I N A R Y
Am79C973/Am79C975
configuration cycle. AD[7:2] select the DWord location
in the configuration space. The Am79C973/Am79C975
controllers ignore AD[10:8], because it is a single func-
tion device. AD[31:11] are don’t care.
The active bytes within a DWord are determined by the
byte enable signals. Eight-bit, 16-bit, and 32-bit trans-
fers are supported. DEVSEL is asserted two clock cy-
c le s af ter t he ho s t h as as s e r te d F R AM E . A ll
c on fi gu rat io n c y c l es a re o f fi xe d le ng th . T h e
Am79C973/Am79C975 controllers will assert TRDY on
the third clock of the data phase.
The Am79C973/Am79C975 controllers do not support
burst transfers for access to configuration space. When
the host keeps FRAME asserted for a second data
phase, the Am79C973/Am79C975 controllers will dis-
connect the transfer.
When the host tries to access the PCI configuration
space while the automatic read of the EEPROM after
H_RESET (see section on RESET) is on-going, the
Am79C973/Am79C975 controllers will terminate the
access on the PCI bus with a disconnect/retry re-
sponse.
The Am79C973/Am79C975 controllers support fast
back-to-back transactions to different targets. This is in-
dicated by the Fast Back-To-Back Capable bit (PCI Sta-
tus register, bit 7), which is hardwired to 1. The
Am79C973/Am79C975 controllers are capable of de-
tecting a configuration cycle even when its address
phase immediately follows the data phase of a transac-
tion to a different target without any idle state in-be-
tween. There will be no contention on the DEVSEL,
TRDY, and STOP signals, since the Am79C973/
Am79C975 controllers assert DEVSEL on the second
clock after FRAME is asserted (medium timing).
Slave I/O Transfers
After the Am79C973/Am79C975 controllers are config-
ured as an I/O device by setting IOEN (for regular I/O
mode) or MEMEN (for memory mapped I/O mode) in
the PCI Command register, it starts monitoring the PCI
bus for access to its CSR, BCR, or APROM locations.
If configured for regular I/O mode, the Am79C973/
Am79C975 controllers will look for an address that falls
within its 32 bytes of I/O address space (starting from
the I/O base address). The Am79C973/Am79C975
controllers assert DEVSEL if it detects an address
match and the access is an I/O cycle. If configured for
m e m o r y m a p p e d I / O m o d e , t h e A m 7 9 C 9 7 3 /
Am79C975 controllers will look for an address that falls
within its 32 bytes of memory address space (starting
from the memory mapped I/O base address). The
AD31
AD11
Don’t care
AD10
AD8
Don’t care
AD7
AD2
DWord
index
AD1
0
AD0
0