AM79C973BKC AMD (ADVANCED MICRO DEVICES), AM79C973BKC Datasheet - Page 106

• Manufacturer Part Number: AM79C973BKC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKC

• Lead Free Status / Rohs Status: Not Compliant

When the Am79C973/Am79C975 controller detects a
Magic Packet frame, it sets the MPMAT bit (CSR116,
b i t 5 ) , t h e M P I N T b i t ( C S R 5 , b i t 4 ) , a n d th e
PME_STATUS bit (PMCSR, bit 15). The setting of the
MPMAT bit will also cause the RWU pin to be asserted
and if the PME_EN or the PME_EN_OVR bits are set,
then the PME will be asserted as well. If IENA (CSR0,
bit 6) and MPINTE (CSR5, bit 3) are set to 1, INTA will
be asserted. Any one of the four LED pins can be pro-
grammed to indicate that a Magic Packet frame has
been received. MPSE (BCR4-7, bit 9) must be set to 1
to enable that function.
Note: The polarity of the LED pin can be programmed
to be active HIGH by setting LEDPOL (BCR4-7, bit 14)
to 1.
O n c e a M ag i c Packe t f r am e i s d e t ec te d , t h e
Am79C973/Am79C975 controller will discard the frame
internally, but will not resume normal transmit and re-
ceive operations until PG is asserted or MPEN is
cleared. Once both of these events has occurred, indi-
cating that the system has detected the Magic Packet
and is awake, the controller will continue polling receive
and transmit descriptor rings where it left off. It is not
necessary to re-initialize the device. If the part is re-ini-
tialized, then the descriptor locations will be reset and
the Am79C973/Am79C975 controller will not start
where it left off.
If magic packet mode is disabled by the assertion of
PG, then in order to immediately re-enable Magic
Packet mode, the PG pin must remain deasserted for
at least 200 ns before it is reasserted. If Magic Packet
mode is disabled by clearing MPEN bit, then it may be
immediately re-enabled by setting MPEN back to 1.
The PCI bus interface clock (CLK) is not required to be
running while the device is operating in Magic Packet
mode. Either of the INTA, the LED pins, RWU or the
PME signal may be used to indicate the receipt of a
Magic Packet frame when the CLK is stopped. If the
system wishes to stop the CLK, it will do so after en-
abling the Magic Packet mode.
CAUTION: To prevent unwanted interrupts from other
active parts of the Am79C973/Am79C975 controller,
care must be taken to mask all likely interruptible
events during Magic Packet mode. An example would
be the interrupts from the Media Independent Interface,
which could occur while the device is in Magic Packet
mode.
IEEE 1149.1 (1990) Test Access Port
Interface
An IEEE 1149.1-compatible boundary scan Test Ac-
cess Port is provided for board-level continuity test and
diagnostics. All digital input, output, and input/output
106
P R E L I M I N A R Y
Am79C973/Am79C975
pins are tested. The following paragraphs summarize
the IEEE 1149.1-compatible test functions imple-
mented in the Am79C973/Am79C975 controller.
Boundary Scan Circuit
The boundary scan test circuit requires four pins (TCK,
TMS, TDI, and TDO), defined as the Test Access Port
(TAP). It includes a finite state machine (FSM), an in-
struction register, a data register array, and a power-on
reset circuit. Internal pull-up resistors are provided for
the TDI, TCK, and TMS pins.
TAP Finite State Machine
The TAP engine is a 16-state finite state machine
(FSM), driven by the Test Clock (TCK), and the Test
Mode Select (TMS) pins. An independent power-on
reset circuit is provided to ensure that the FSM is in the
TEST_LOGIC_RESET state at power-up. Therefore,
the TRST is not provided. The FSM is also reset when
TMS and TDI are high for five TCK periods.
Supported Instructions
In addition to the minimum IEEE 1149.1 requirements
(BYPASS, EXTEST, and SAMPLE instructions), three
additional instructions (IDCODE, TRIBYP, and SET-
BYP) are provided to further ease board-level testing.
All unused instruction codes are reserved. See Table
16 for a summary of supported instructions.
Instruction Register and Decoding Logic
After the TAP FSM is reset, the IDCODE instruction is
always invoked. The decoding logic gives signals to con-
trol the data flow in the Data registers according to the
current instruction.
Boundary Scan Register
Each Boundary Scan Register (BSR) cell has two
stages. A flip-flop and a latch are used for the Serial
Shift Stage and the Parallel Output Stage, respectively.
Instruction
SAMPLE
SETBYP
EXTEST
IDCODE
BYPASS
TRIBYP
Name
Table 16. IEEE 1149.1 Supported Instruction
Instruction
Code
0000
0001
0010
0011
0100
1111
Summary
Bypass Scan Normal
External Test
Boundary To
Description
Force Float
Inspection
Boundary
ID Code
Sample
Control
1/0
Normal
Normal
Normal
Mode
Test
Test
Selected
Register
ID REG
Bypass
Bypass
Bypass
Data
BSR
BSR