AM79C973BKC AMD (ADVANCED MICRO DEVICES), AM79C973BKC Datasheet - Page 124

• Manufacturer Part Number: AM79C973BKC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKC

• Lead Free Status / Rohs Status: Not Compliant

11
10
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MERR
RINT
bit MISSM (CSR3, bit 12) is 0.
MISS assertion will set the ERR
bit, regardless of the settings of
IENA and MISSM.
Read/Write accessible always.
MISS is cleared by the host by
writing a 1. Writing a 0 has no ef-
fect.
H_RESET, S_RESET, or by set-
ting the STOP bit.
Am79C973/Am79C975 controller
when it requests the use of the
system interface bus by asserting
REQ and has not received GNT
assertion after a programmable
length of time. The length of time
in microseconds before MERR is
asserted will depend upon the
setting of the Bus Timeout Regis-
ter (CSR100). The default setting
of CSR100 will give a MERR after
153.6 ms of bus latency.
When MERR is set, INTA is as-
serted if IENA is 1 and the mask
bit MERRM (CSR3, bit 11) is 0.
MERR assertion will set the ERR
bit, regardless of the settings of
IENA and MERRM.
Read/Write accessible always.
MERR is cleared by the host by
writing a 1. Writing a 0 has no ef-
fect.
H_RESET, S_RESET, or by set-
ting the STOP bit.
Am79C973/Am79C975 controller
after the last descriptor of a re-
ceive frame has been updated by
writing a 0 to the OWNership bit.
RINT may also be set when the
first descriptor of a receive frame
has been updated by writing a 0
to the OWNership bit if the LAP-
PEN bit of CSR3 has been set to
a 1.
When RINT is set, INTA is assert-
ed if IENA is 1 and the mask bit
RINTM (CSR3, bit 10) is 0.
Read/Write accessible always.
RINT is cleared by the host by
writing a 1. Writing a 0 has no ef-
Memory Error is set by the
Receive Interrupt is set by the
MERR
MISS
is
is
cleared
cleared
P R E L I M I N A R Y
Am79C973/Am79C975
by
by
9
8
7
TINT
IDON
INTR
fect.
H_RESET, S_RESET, or by set-
ting the STOP bit.
When TINT is set, INTA is assert-
ed if IENA is 1 and the mask bit
TINTM (CSR3, bit 9) is 0.
TINT will not be set if TINTOKD
(CSR5, bit 15) is set to 1 and the
transmission was successful.
Read/Write accessible always.
TINT is cleared by the host by
writing a 1. Writing a 0 has no ef-
fect.
H_RESET, S_RESET, or by set-
ting the STOP bit.
When IDON is set, INTA is as-
serted if IENA is 1 and the mask
bit IDONM (CSR3, bit 8) is 0.
Read/Write accessible always.
IDON is cleared by the host by
writing a 1. Writing a 0 has no ef-
fect.
H_RESET, S_RESET, or by set-
ting the STOP bit.
Transmit Interrupt is set by the
Am79C973/Am79C975 controller
after the OWN bit in the last de-
scriptor of a transmit frame has
been cleared to indicate the
frame has been sent or an error
occurred in the transmission.
Initialization Done is set by the
Am79C973/Am79C975 controller
after the initialization sequence
has completed. When IDON is
set, the Am79C973/Am79C975
controller has read the initializa-
tion block from memory.
Interrupt Flag indicates that one
or more following interrupt caus-
ing conditions has occurred:
EXDINT, IDON, MERR, MISS,
MFCO, RCVCCO, RINT, SINT,
TINT, TXSTRT, UINT, STINT,
MREINT, MCCINT, MIIPDTINT,
MAPINT and the associated
mask or enable bit is pro-
grammed to allow the event to
cause an interrupt. If IENA is set
to 1 and INTR is set, INTA will be
active. When INTR is set by SINT
RINT
IDON
TINT
is
is
is
cleared
cleared
cleared
by
by
by