AM79C973BKC AMD (ADVANCED MICRO DEVICES), AM79C973BKC Datasheet - Page 144

• Manufacturer Part Number: AM79C973BKC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKC

• Lead Free Status / Rohs Status: Not Compliant

31-16 RES
15-12 RES
11-0
CSR45: Next Receive Status
Bit
31-16 RES
15-0
CSR46: Transmit Poll Time Counter
Bit
31-16 RES
15-0
CSR47: Transmit Polling Interval
Bit
31-16 RES
144
NRBC
NRST
TXPOLL
Name
Name
Name
Reserved locations. Written as
zeros and read as undefined.
Reserved locations. Read and
written as zeros.
Next Receive Byte Count. This
field is a copy of the BCNT field of
RMD1 of the next receive de-
scriptor.
Reserved locations. Written as
zeros and read as undefined.
Next Receive Status. This field is
a copy of bits 31-16 of RMD1 of
the next receive descriptor.
Reserved locations. Written as
zeros and read as undefined.
Transmit Poll Time Counter. This
counter is incremented by the
Am79C973/Am79C975 controller
microcode and is used to trigger
the transmit descriptor ring poll-
ing operation of the Am79C973/
Am79C975 controller.
Reserved locations. Written as
zeros and read as undefined.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
Description
Description
Description
P R E L I M I N A R Y
Am79C973/Am79C975
15-0 TXPOLLINT
Transmit Polling Interval. This
register contains the time that the
Am79C973/Am79C975 controller
will wait between successive poll-
ing operations. The TXPOLLINT
value is expressed as the two’s
complement of the desired inter-
val, where each bit of TXPOL-
LINT represents 1 clock period of
time. TXPOLLINT[3:0] are ig-
nored. (TXPOLLINT[16] is im-
plied
TXPOLLINT[15] is significant and
does not represent the sign of the
two’s complement TXPOLLINT
value.)
The default value of this register
is 0000h. This corresponds to a
polling interval of 65,536 clock
periods
CLK = 33 MHz). The TXPOL-
LINT value of 0000h is created
during the microcode initialization
routine and, therefore, might not
be seen when reading CSR47 af-
ter H_RESET or S_RESET.
If the user desires to program a
value for POLLINT other than the
default, then the correct proce-
dure is to first set INIT only in
CSR0. Then, when the initializa-
tion sequence is complete, the
user must set STOP (CSR0, bit
2). Then the user may write to
CSR47 and then set STRT in
CSR0. In this way, the default
value of 0000h in CSR47 will be
overwritten with the desired user
value.
If the user does not use the stan-
dard
(standard implies use of an initial-
ization block in memory and set-
ting the INIT bit of CSR0), but
instead, chooses to write directly
to each of the registers that are
involved in the INIT operation,
then it is imperative that the user
also writes all zeros to CSR47 as
part of the alternative initialization
sequence.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
to
initialization
(1.966
be
a
ms
procedure
one,
when
so