AM79C973BKC AMD (ADVANCED MICRO DEVICES), AM79C973BKC Datasheet - Page 137

• Manufacturer Part Number: AM79C973BKC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKC

• Lead Free Status / Rohs Status: Not Compliant

CSR10: Logical Address Filter 2
Bit
31-16
15-0 LADRF[47:32] Logical
CSR11: Logical Address Filter 3
Bit
31-16
15-0 LADRF[63:48] Logical
CSR12: Physical Address Register 0
Note: Bits 15-0 in this register are programmable
through the EEPROM.
Bit
31-16
Name
RES
Name
RES
Name
RES
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
zeros and read as undefined.
LADRF[47:32]. The content of
this register is undefined until
loaded from the initialization
block after the INIT bit in CSR0
has been set or a direct register
write has been performed on this
register.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
zeros and read as undefined.
LADRF[63:48]. The content of
this register is undefined until
loaded from the initialization
block after the INIT bit in CSR0
has been set or a direct register
write has been performed on this
register.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
zeros and read as undefined.
Description
Reserved locations. Written as
Description
Reserved locations. Written as
Description
Reserved locations. Written as
Address
Address
P R E L I M I N A R Y
Am79C973/Am79C975
Filter,
Filter,
15-0
CSR13: Physical Address Register 1
Note: Bits 15-0 in this register are programmable
through the EEPROM.
Bit
31-16 RES
15-0
CSR14: Physical Address Register 2
Note: Bits 15-0 in this register are programmable
through the EEPROM.
Bit
PADR[15:0] Physical
Name
PADR[31:16]Physical
Name
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
PADR[15:0]. The contents of this
register are loaded from EE-
PROM after H_RESET or by an
EEPROM
(PRGAD, BCR19, bit 14). If the
EEPROM is not present, the con-
tents of this register are unde-
fined.
This register can also be loaded
from the initialization block after
the INIT bit in CSR0 has been set
or a direct register write has been
performed on this register.
Description
Reserved locations. Written as
zeros and read as undefined.
PADR[31:16]. The contents of
this register are loaded from EE-
PROM after H_RESET or by an
EEPROM
(PRGAD, BCR19, bit 14). If the
EEPROM is not present, the con-
tents of this register are unde-
fined.
This register can also be loaded
from the initialization block after
the INIT bit in CSR0 has been set
or a direct register write has been
performed on this register.
Description
Address
Address
read
read
command
command
Register,
Register,
137