AM79C973BKC AMD (ADVANCED MICRO DEVICES), AM79C973BKC Datasheet - Page 157

• Manufacturer Part Number: AM79C973BKC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKC

• Lead Free Status / Rohs Status: Not Compliant

7-0
IFS1
Note: Programming of the IPG
should be done in nibble intervals
instead of absolute bit times. The
decimal and hex values do not
match due to delays in the part
used to make up the final IPG.
Changes should be added or sub-
tracted from the provided hex val-
ue on a one-for-one basis.
gressive nodes to defer. By pro-
gramming a larger number of bit
times,
Am79C975 MAC will become
less aggressive on the network
and may defer more often than
normal. The performance of the
Am79C973/Am79C975 controller
may decrease as the IPG value is
increased from the default value.
InterFrameSpacingPart1. Chang-
ing IFS1 allows the user to pro-
gram the value of the InterFrame-
SpacePart1
Am79C973/Am79C975 controller
sets the default value at 60 bit
times (3ch). See the subsection
on Medium Allocation in the sec-
tion Media Access Management
for more details.
The equation for setting IFS1
when IPG
lows:
CAUTION: Use this parameter
with care. By lowering the IPG
below the ISO/IEC 8802-3 stan-
dard
Am79C973/Am79C975 control-
ler can interrupt normal net-
work behavior.
Read/Write is accessible only
when either the STOP bit or the
SPND bit is set. IPG is set to 60h
(96 Bit times) by H_RESET or
S_RESET and is not affected by
STOP.
IFS1 = IPG - 36 bit times
Note: Programming of the IPG
should be done in nibble intervals
instead of absolute bit times due
to the MII. The decimal and hex
96
the
96 bit times is as fol-
bit
timing.
times,
Am79C973/
P R E L I M I N A R Y
Am79C973/Am79C975
The
the
Bus Configuration Registers
The Bus Configuration Registers (BCR) are used to
program the configuration of the bus interface and oth-
er special features of the Am79C973/Am79C975 con-
troller that are not related to the IEEE 8802-3 MAC
functions. The BCRs are accessed by first setting the
appropriate RAP value and then by performing a slave
access to the BDP. See Table 29.
All BCR registers are 16 bits in width in Word I/O mode
(DWIO = 0, BCR18, bit 7) and 32 bits in width in DWord
I/O mode (DWIO = 1). The upper 16 bits of all BCR reg-
isters is undefined when in DWord I/O mode. These
bits should be written as zeros and should be treated
as undefined when read. The default value given for
any BCR is the value in the register after H_RESET.
Some of these values may be changed shortly after
H_RESET when the contents of the external EEPROM
is automatically read in. None of the BCR register val-
ues are affected by the assertion of the STOP bit or
S_RESET.
Note that several registers have no default value.
BCR0, BCR1, BCR3, BCR8, BCR10-17, and BCR21
are reserved and have undefined values. BCR2 and
BCR34 are not observable without first being pro-
grammed through the EEPROM read operation or a
user register write operation.
BCR0, BCR1, BCR16, BCR17, and BCR21 are regis-
ters that are used by other devices in the PCnet family.
Writing to these registers have no effect on the opera-
tion of the Am79C973/Am79C975 controller.
Writes to those registers marked as “Reserved” will
have no effect. Reads from these locations will produce
undefined values.
values do not match due to de-
lays in the part used to make up
the final IPG.
Changes should be added or
subtracted from the provided hex
value on a one-for-one basis.
Due to changes in synchroniza-
tion delays internally through dif-
ferent network ports, the IFS1
can be off by as much as +12 bit
times.
Read/Write is accessible only
when either the STOP bit or the
SPND bit is set. IFS1 is set to 3ch
(60 bit times) by H_RESET or
S_RESET and is not affected by
STOP.
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