AM79C973BKC AMD (ADVANCED MICRO DEVICES), AM79C973BKC Datasheet - Page 128

• Manufacturer Part Number: AM79C973BKC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKC

• Lead Free Status / Rohs Status: Not Compliant

128
host for each packet, and not all
messages may need all of the de-
scriptors that are allocated be-
tween descriptors that contain
STP = 1, then some descriptors/
buffers may be skipped in the
ring. While performing the search
for the next STP bit that is set to
1,
controller will advance through
the receive descriptor ring re-
gardless of the state of ownership
bits. If any of the entries that are
examined during this search indi-
cate Am79C973/Am79C975 con-
troller ownership of the descriptor
but also indicate STP = 0, then
the Am79C973/Am79C975 con-
troller will reset the OWN bit to 0
in these entries. If a scanned en-
try indicates host ownership with
STP = 0, then the Am79C973/
Am79C975 controller will not al-
ter the entry, but will advance to
the next entry.
When the STP bit is found to be
true, but the descriptor that con-
tains this setting is not owned by
the Am79C973/Am79C975 con-
troller,
Am79C975 controller will stop
advancing through the ring en-
tries and begin periodic polling of
this entry. When the STP bit is
found to be true, and the descrip-
tor that contains this setting is
owned
Am79C975 controller, then the
Am79C973/Am79C975 controller
will stop advancing through the
ring entries, store the descriptor
information that it has just read,
and wait for the next receive to ar-
rive.
This behavior allows the host
software to pre-assign buffer
space in such a manner that the
header portion of a receive pack-
et will always be written to a par-
ticular memory area, and the data
portion of a receive packet will al-
ways be written to a separate
memory area. The interrupt is
generated when the header bytes
have been written to the header
memory area.
the
then
by
Am79C973/Am79C975
the
the
Am79C973/
Am79C973/
P R E L I M I N A R Y
Am79C973/Am79C975
4
3
2
DXMT2PD Disable Transmit Two Part Defer-
EMBA
BSWP
Read/Write accessible always.
The LAPPEN bit will be reset to 0
by H_RESET or S_RESET and
will be unaffected by STOP.
See Appendix E for more infor-
mation on the Look Ahead Pack-
et Processing concept.
Read/Write accessible always.
DXMT2PD
H_RESET or S_RESET and is
not affected by STOP.
Read/Write accessible always.
EMBA is cleared by H_RESET or
S_RESET and is not affected by
STOP.
When big Endian mode is select-
ed, the Am79C973/Am79C975
controller will swap the order of
bytes on the AD bus during a data
phase on accesses to the FIFOs
only. Specifically, AD[31:24] be-
comes Byte 0, AD[23:16] be-
comes Byte 1, AD[15:8] becomes
Byte 2, and AD[7:0] becomes
Byte 3 when big Endian mode is
selected. When
mode is selected, the order of
bytes on the AD bus during a data
phase is: AD[31:24] is Byte 3,
AD[23:16] is Byte 2, AD[15:8] is
Byte 1, and AD[7:0] is Byte 0.
ral (see Medium Allocation sec-
tion
Management section for more
details). If DXMT2PD is set,
Transmit Two Part Deferral will
be disabled.
Enable Modified Back-off Algo-
rithm (see Contention Resolution
section in Media Access Man-
agement section for more de-
tails). If EMBA is set, a modified
back-off algorithm is implement-
ed.
Byte Swap. This bit is used to
choose between big and little En-
dian modes of operation. When
BSWP is set to a 1, big Endian
mode is selected. When BSWP is
set to 0, little Endian mode is se-
lected.
in
the
is
Media
cleared
little
Access
Endian
by