AM79C973BKC AMD (ADVANCED MICRO DEVICES), AM79C973BKC Datasheet - Page 152

• Manufacturer Part Number: AM79C973BKC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKC

• Lead Free Status / Rohs Status: Not Compliant

CSR82: Transmit Descriptor Address Pointer
Lower
Bit
31-16 RES
15-0
CSR84: DMA Address Register Lower
Bit
31-16 RES
15-0
152
TXDAPL
DMABAL
Name
Name
Reserved locations. Written as
zeros and read as undefined.
Contains the lower 16 bits of the
transmit descriptor address cor-
responding to the last buffer of
the previous transmit frame. If the
previous transmit frame did not
use buffer chaining, then TXDA-
PL contains the lower 16 bits of
the previous frame’s transmit de-
scriptor address.
Reserved locations. Written as
zeros and read as undefined.
This register contains the lower
16 bits of the address of system
memory for the current DMA cy-
cle. The Bus Interface Unit con-
trols the Address Register by
issuing increment commands to
increment the memory address
for sequential operations. The
DMABAL register is undefined
until
Am79C975 controller DMA oper-
ation.
When both the STOP or SPND
bits are cleared, this register is
updated
Am79C975 controller immediate-
ly before a transmit descriptor
write.
Read accessible always. Write
accessible through the PXDAL
bits (CSR60) when the STOP or
SPND bit is set. TXDAPL is set to
0 by H_RESET and are unaffect-
ed by S_RESET or STOP.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
Description
Description
the
by
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Am79C973/
Am79C973/
P R E L I M I N A R Y
Am79C973/Am79C975
CSR85: DMA Address Register Upper
Bit
31-16 RES
15-0
CSR86: Buffer Byte Counter
Bit
31-16 RES
15-12 RES
11-0
CSR88: Chip ID Register Lower
Bit
31-28 VER
DMABAU
DMABC
Name
Name
Name
Reserved locations. Written as
zeros and read as undefined.
This register contains the upper
16 bits of the address of system
memory for the current DMA cy-
cle. The Bus Interface Unit con-
trols the Address Register by
issuing increment commands to
increment the memory address
for sequential operations. The
DMABAU register is undefined
until
Am79C975 controller DMA oper-
ation.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
Reserved locations. Written as
zeros and read as undefined.
Reserved. Read and written with
ones.
DMA Byte Count Register. Con-
tains the two's complement of the
current size of the remaining
transmit or receive buffer in
bytes. This register is increment-
ed by the Bus Interface Unit. The
DMABC register is undefined un-
til written.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
Version. This 4-bit pattern is
silicon-revision dependent.
Read accessible only when either
the STOP or the SPND bit is set.
Description
Description
Description
the
first
Am79C973/