AM79C973BKC AMD (ADVANCED MICRO DEVICES), AM79C973BKC Datasheet - Page 133

• Manufacturer Part Number: AM79C973BKC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKC

• Lead Free Status / Rohs Status: Not Compliant

CSR6: RX/TX Descriptor Table Length
Bit
31-16
15-12
11-8
Name
RES
TLEN
RLEN
In suspend mode, all of the CSR
and BCR registers are accessi-
ble. As long as the Am79C973/
Am79C975 controller is not reset
while in suspend mode (by
H_RESET, S_RESET or by set-
ting the STOP bit), no re-initial-
ization of the device is required
after the device comes out of sus-
pend mode. The Am79C973/
Am79C975 controller will contin-
ue at the transmit and receive de-
scriptor
where it had left, when it entered
the suspend mode.
Read/Write accessible always.
SPND is cleared by H_RESET,
S_RESET, or by setting the
STOP bit.
zeros and read as undefined.
encoded ring length (TLEN) field
read from the initialization block
during
Am79C975 controller initializa-
tion. This field is written during
the Am79C973/Am79C975 con-
troller initialization routine.
Read accessible only when either
the STOP or the SPND bit is set.
Write operations have no effect
and should not be performed.
TLEN is only defined after initial-
ization. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
encoded ring length (RLEN) read
from the initialization block during
Am79C973/Am79C975 controller
initialization. This field is written
during
Am79C975 controller initializa-
tion routine.
Read accessible only when either
the STOP or the SPND bit is set.
Write operations have no effect
and should not be performed.
Description
Reserved locations. Written as
Contains a copy of the transmit
Contains a copy of the receive
ring
the
the
locations,
Am79C973/
Am79C973/
P R E L I M I N A R Y
Am79C973/Am79C975
from
7-0
CSR7: Extended Control and Interrupt 2
Certain bits in CSR7 indicate the cause of an interrupt.
The register is designed so that these indicator bits are
cleared by writing ones to those bit locations. This
means that the software can read CSR7 and write back
the value just read to clear the interrupt condition.
Bit
31-16 RES
15
FASTSPNDE Fast Suspend Enable. When
RES
Name
RLEN is only defined after initial-
ization. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
When FASTSPNDE is 0 and the
SPND bit is set, the Am79C973/
Am79C975 controller may take
longer before entering the sus-
pend mode. At the time the
SPND bit is set, the Am79C973/
Am79C975 controller will com-
plete the DMA process of a trans-
mit packet if it had already begun
Reserved locations. Read as 0s.
Write operations are ignored.
Description
Reserved locations. Written as
zeros and read as undefined.
FASTSPNDE is set to 1, the
Am79C973/Am79C975 controller
performs a fast suspend whenev-
er the SPND bit is set.
When a fast suspend is request-
ed, the Am79C973/Am79C975
controller performs a quick entry
into the suspend mode. At the
time the SPND bit is set, the
Am79C973/Am79C975 controller
will complete the DMA process of
any transmit and/or receive pack-
et that had already begun DMA
activity. In addition, any transmit
packet that had started transmis-
sion will be fully transmitted and
any receive packet that had be-
gun reception will be fully re-
ceived. However, no additional
packets will be transmitted or re-
ceived and no additional transmit
or receive DMA activity will begin.
Hence,
Am79C975 controller may enter
the suspend mode with transmit
and/or receive packets still in the
FIFOs or the SRAM.
the
Am79C973/
133