AM79C973BKC AMD (ADVANCED MICRO DEVICES), AM79C973BKC Datasheet - Page 130

• Manufacturer Part Number: AM79C973BKC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKC

• Lead Free Status / Rohs Status: Not Compliant

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MFCO
MFCOM
UINTCMD
UINT
RCVCCO
is
Am79C975 controller when the
Missed Frame Counter (CSR112
and
around.
When MFCO is set, INTA is as-
serted if IENA is 1 and the mask
bit MFCOM is 0.
Read/Write accessible always.
MFCO is cleared by the host by
writing a 1. Writing a 0 has no ef-
fect.
H_RESET, S_RESET, or by set-
ting the STOP bit.
Mask. If MFCOM is set, the
MFCO bit will be masked and un-
able to set the INTR bit.
Read/Write accessible always.
MFCOM is set to 1 by H_RESET
or S_RESET and is not affected
by the STOP bit.
UINTCMD can be used by the
host to generate an interrupt un-
related to any network activity.
When UINTCMD is set, INTA is
asserted if IENA is set to 1.
UINTCMD will be cleared inter-
nally
Am79C975 controller has set
UINT to 1.
Read/Write accessible always.
UINTCMD
H_RESET or S_RESET or by
setting the STOP bit.
Am79C973/Am79C975 controller
after the host has issued a user
interrupt command by setting
UINTCMD (CSR4, bit 7) to 1.
Read/Write accessible always.
UINT is cleared by the host by
writing a 1. Writing a 0 has no ef-
fect.
H_RESET or S_RESET or by
setting the STOP bit.
flow is set by the Am79C973/
Missed Frame Counter Overflow
Missed Frame Counter Overflow
User
User Interrupt. UINT is set by the
Receive Collision Counter Over-
set
CSR113)
MFCO
UINT
after
Interrupt
by
is
the
the
is
is
has
cleared
cleared
cleared
Am79C973/
Am79C973/
P R E L I M I N A R Y
Command.
Am79C973/Am79C975
wrapped
by
by
by
4
3
2
1-0
CSR5: Extended Control and Interrupt 1
Certain bits in CSR5 indicate the cause of an interrupt.
The register is designed so that these indicator bits are
cleared by writing ones to those bit locations. This
RCVCCOM Receive Collision Counter Over-
TXSTRT
TXSTRTM
RES
When RCVCCO is set, INTA is
asserted if IENA is 1 and the
mask bit RCVCCOM is 0.
Read/Write accessible always.
RCVCCO is cleared by the host
by writing a 1. Writing a 0 has no
effect. RCVCCO is cleared by
H_RESET, S_RESET, or by set-
ting the STOP bit.
Read/Write accessible always.
RCVCCOM is set to 1 by
H_RESET or S_RESET and is
not affected by the STOP bit.
When TXSTRT is set, INTA is as-
serted if IENA is 1 and the mask
bit TXSTRTM is 0.
Read/Write accessible always.
TXSTRT is cleared by the host by
writing a 1. Writing a 0 has no ef-
fect. TXSTRT is cleared by
H_RESET, S_RESET, or by set-
ting the STOP bit.
Read/Write accessible always.
TXSTRTM
H_RESET or S_RESET and is
not affected by the STOP bit.
Am79C975 controller when the
Receive
(CSR114 and CSR115)
wrapped around.
flow Mask. If RCVCCOM is set,
the RCVCCO bit will be masked
and unable to set the INTR bit.
Transmit Start status is set by the
Am79C973/Am79C975 controller
whenever it begins transmission
of a frame.
Transmit Start Mask. If TX-
STRTM is set, the TXSTRT bit
will be masked and unable to set
the INTR bit.
Reserved locations. Written as
zeros and read as undefined.
Collision
is
set
to
Counter
1
has
by