B69000 Asiliant Technologies, B69000 Datasheet - Page 122

• Manufacturer Part Number: B69000
• Manufacturer: Asiliant Technologies

Specifications of B69000

• Lead Free Status / Rohs Status: Supplier Unconfirmed

CR30
read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 30h
7-4
3-0
CR31
read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 31h
7-4
3-0
&+,36
7
7
Reserved
These bits should always be written with the value of 0.
Vertical Total Bits 11-8
The vertical total is a 10-bit or 12-bit value that specifies the total number of scanlines. This includes
the scanlines both inside and outside of the active display area.
Reserved
These bits should always be written with the value of 0.
Vertical Display End Bits 11-8
The vertical display enable end is a 10-bit or 12-bit value that specifies the number of the last
scanline within the active display area.
69000 Databook
Extended Vertical Total Register
Extended Vertical Display End Register
In standard VGA modes, where bit 0 of the I/O Control Register (XR09) is set to 0, the
vertical total is specified with a 10-bit value. The 8 least significant bits of the vertical total
are supplied by bits 7-0 of the Vertical Total Register (CR06), and the 2 most significant bits
are supplied by bits 5 and 0 of the Overflow Register (CR07). In standard VGA modes,
these bits 3-0 of this register (CR30) are not used.
In extended modes, where bit 0 of the I/O Control Register (XR09) is set to 1, the vertical
total is specified with a 12-bit value. The 8 least significant bits of this value are supplied
by bits 7-0 of the Vertical Total Register (CR06), and the 4 most significant bits are supplied
by bits 3-0 of this register (CR30).
This 10-bit or 12-bit value should be programmed to be equal to the total number of
scanlines, minus 2.
In standard VGA modes, where bit 0 of the I/O Control Register (XR09) is set to 0, the
vertical display enable end is specified with a 10-bit value. The 8 least significant bits of
the vertical display enable end are supplied by bits 7-0 of the Vertical Display Enable End
Register (CR12), and the 2 most significant bits are supplied by bits 6 and 1 of the Overflow
Register (CR07). In standard VGA modes bits 3-0 of CR31 are not used.
In extended modes, where bit 0 of the I/O Control Register (XR09) is set to 1, the vertical
display enable end is specified with a 12-bit value. The 8 least significant bits of the vertical
display enable end are supplied by bits 7-0 of the Vertical Display Enable End Register
(CR12), and the 4 most significant bits are supplied by these 4 bits of this register (CR31).
This 10-bit or 12-bit value should be programmed to be equal to the number of the last
scanline with in the active display area. Since the active display area always starts on the
0th scanline, this number should be equal to the total number of scanlines within the active
display area, minus 1.
6
6
Reserved
Reserved
5
5
Subject to Change Without Notice
CRT Controller Registers
4
4
3
3
Vertical Display End Bits 11-8
Vertical Total Bits 11-8
2
2
Revision 1.3 8/31/98
1
1
0
0
9-29