B69000 Asiliant Technologies, B69000 Datasheet - Page 133

• Manufacturer Part Number: B69000
• Manufacturer: Asiliant Technologies

Specifications of B69000

• Lead Free Status / Rohs Status: Supplier Unconfirmed

9-40
CR77
read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 77h
7
6-4
3
Note: Bits 1 and 0 of this register must both be set to 1 in order to enable the flicker reduction filtering
2
Note:
1
0
Note:
&+,36
Line Halving
Text Mode
(0)
7
VGA Text Mode Scanline Halving
Reserved (Writable)
These bits should always be written with the value of 0.
Horizontal Flicker Reduction Filtering Enable
hardware, before horizontal flicker reduction filtering can be enabled through this bit.
0: Disables horizontal flicker reduction filtering
1: Enables horizontal flicker reduction filtering where the current pixel is averaged with the pixels
immediately to the left and right on the same scanline. This averaging process uses weighted
averaging. The current pixel’s value is divided by 2, the values of each of the two adjacent pixels
is divided by 4, and the resulting three values are added to create the value that is displayed.
Vertical Flicker Reduction Filtering Enable
Bits 1 and 0 of this register must both be set to 1 in order to enable the flicker reduction filtering
hardware, before vertical flicker reduction filtering can be enabled through this bit.
0: Disables vertical flicker reduction filtering
1: Enables vertical flicker reduction filtering where the pixels of the current scanline are averaged
with the pixels of the next scanline as the pixels of the current scanline are being displayed.
Internal Clock Doubling Enable
0: One of the internal clocks used by the graphics controller remains at normal clock rates.
1: One of the internal clocks used by the graphics controller is doubled in frequency.
Flicker Reduction Filtering Enable
Bit 1 of this register should be set to enable the doubling of an internal clock, before the use of the
flicker reduction hardware is enabled by setting this bit to 1.
0: Disables all flicker reduction filter hardware.
1: Enables the use of the flicker reduction filter hardware.
69000 Databook
NTSC/PAL Filtering Control Register
0: Disables VGA text mode scanline halving.
1: Enables VGA text mode scanline halving, where the setting carried in the Maximum
Scanline Register (CR09) and that carried by bits 4-0 of the Text Cursor End Register
(CR0B) are halved. This is done to cut the number of scanlines actually sent to the display
from VGA standard quantities (such as 400) down to quantities that are more manageable
for televisions (such as 200) without actually programming CR09 and bits 4-0 of CR0B with
values that are different from VGA standards. This function is meant to be used in
conjunction with character fonts that are only half as high as those normally used in VGA
text modes.
6
Reserved (Writable)
(000)
5
Subject to Change Without Notice
CRT Controller Registers
4
Hor. Filter
Enable
(0)
3
Ver. Filter
Enable
(0)
2
Clk Doubling
Enable
(0)
Revision 1.3 8/31/98
1
Filtering
Enable
(0)
0