B69000 Asiliant Technologies, B69000 Datasheet - Page 77

• Manufacturer Part Number: B69000
• Manufacturer: Asiliant Technologies

Specifications of B69000

• Lead Free Status / Rohs Status: Supplier Unconfirmed

DEVSTAT
read/write at PCI configuration offset 06h
byte or word accessible
accessible only via PCI configuration cycles
Important: Read accesses to this register behave normally. Writes, however, behave differently in that
bits can be reset to 0, but not set to 1. A bit in this register is reset to 0 whenever it is written with the value
of 1. Bits written with a value of 0 are entirely unaffected.
15
Note:
14
Note:
13
12
11
&+,36
Parity
Error
Det
(0)
15
System
Signal
Error
Detected Parity Error
0: No address or data parity error detected.
1: An address or data parity error was detected.
This bit is set in response to a parity error regardless of the settings of either bit 6 (Parity Error
Response bit) and 8 (SERR# Enable) of the Device Control Register (DEVCTL).
Signaled System Error
0: SERR# has not been asserted.
1: SERR# has been asserted.
Both bits 6 (Parity Error Response bit) and 8 (SERR# Enable) of the Device Control Register
(DEVCTL) must both be set to 1 to enable the use of SERR# and the setting of this bit to 1 in
response to an address parity error.
Received Master Abort
This bit applies only to PCI Bus masters. Since the 69000 never functions as a PCI Bus master,
this bit always returns a value of 0 when read.
Received Target Abort
This bit applies only to PCI Bus masters. Since the 69000 never functions as a PCI Bus master,
this bit always returns a value of 0 when read.
Signaled Target Abort
0: A target abort was not generated.
1: A target abort was generated.
A target abort can be generated by the 69000 on I/O cycles with non-adjacent active byte enables.
(0)
14
69000 Databook
Master
Abort
Rcvd
(0)
13
Target
Abort
Rcvd
Device Status Register
(0)
12
Target
Signal
Abort
(0)
11
10
DEVSEL#
Subject to Change Without Notice
Timing
(01)
PCI Configuration Registers
9
Parity
Error
Data
(0)
8
Back-
Back
Fast
(1)
7
UDF
(0)
6
MHz
(0)
66
5
4
3
Revision 1.3 8/31/98
Reserved
(0:0000)
2
1
0
7-5