B69000 Asiliant Technologies, B69000 Datasheet - Page 99

• Manufacturer Part Number: B69000
• Manufacturer: Asiliant Technologies

Specifications of B69000

• Lead Free Status / Rohs Status: Supplier Unconfirmed

9-6
CR05
read/write at I/O address 3B5h/3D5h with index at address 3B4h/3D4h set to 05h
7
6-5
4-0
&+,36
Hor Blnk End
Bit 5
7
Horizontal Blanking End Bit 5
This bit provides either the most significant bit of a 6-bit value or the 3rd most significant bit of an 8-
bit value that specifies the end of the horizontal blanking period relative to its beginning.
In standard VGA modes, where bit 0 of the I/O Control Register (XR09) is set to 0, the horizontal
blanking end is specified with a 6-bit value. The 5 least significant bits of this value are supplied by
bits 4-0 of the Horizontal Blanking End Register (CR03), and the most significant bit is supplied by
this bit of this register.
In extended modes, where bit 0 of the I/O Control Register (XR09) is set to 1, the horizontal blanking
end is specified with an 8-bit value. The 5 least significant bits of this value are supplied by bits 4-
0 of the Horizontal Blanking End Register (CR03), the next most significant bit is supplied by this
bit of this register, and the 2 most significant bits are supplied by bits 7 and 6 of the Extended
Horizontal Blanking End Register (CR3C).
This 6-bit or 8-bit value should be programmed to be equal to the least significant 6 or 8 bits,
respectively, of the result of adding the length of the blanking period in terms of character clocks to
the value specified in the Horizontal Blanking Start Register (CR02).
Horizontal Sync Delay
These bits define the degree to which the start and end of the horizontal sync pulse are delayed to
compensate for internal pipeline delays.
These 2 bits describe the delay in terms of a number of character clocks.
Horizontal Sync End
These 5 bits provide the 5 least significant bits of a 6-bit value that specifies the end of the horizontal
sync pulse relative to its beginning. In other words, this 6-bit value specifies the width of the
horizontal sync pulse. Bit 7 of Horizontal Sync End Register (CR05) supplies the most significant
bit.
This 6-bit value should be set to the least significant 6 bits of the result of adding the width of the
sync pulse in terms of character clocks to the value specified in the Horizontal Sync Start Register
(CR04).
69000 Databook
Horizontal Sync End Register
Horizontal Sync Delay
6
5
6 5
0 0
0 1
1 0
1 1
Bit
Subject to Change Without Notice
CRT Controller Registers
delayed by 2 character clocks
delayed by 3 character clocks
delayed by 1 character clock
4
Amount of Delay
no delay
3
Horizontal Sync End
2
Revision 1.3 8/31/98
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