B69000 Asiliant Technologies, B69000 Datasheet - Page 205

• Manufacturer Part Number: B69000
• Manufacturer: Asiliant Technologies

Specifications of B69000

• Lead Free Status / Rohs Status: Supplier Unconfirmed

14-38
XRC3
read/write at I/O address 3D7h with index at I/O address 3D6h set to C3h
Note: All four of the registers used in specifying the loop parameters for dot clock 0 (XRC0 - XRC3) must
be written, and in order from XRC0 to XRC3, before the hardware will update the synthesizer’s settings.
This is a form of double-buffering that is intended to prevent fluctuations in the synthesizer’s output as new
values are being written to these registers.
7
6-4
3
2
1-0
&+,36
Reserved
7
Reserved
This bit always returns the value of 0 when read.
Post Divisor Select
These three bits select a value that specifies the post divisor, one of the loop parameters used in
controlling the frequency of the output of the synthesizer used to generate dot clock 0. The manner
in which these bits are used to choose this value is shown in the table below:
Reserved
VCO Loop Divisor Select
Reserved
69000 Databook
Dot Clock 0 Divisor Select Register
A series of calculations are used to derive this value and the values for the other loop
parameters given a desired output frequency and a series of constraints placed on different
components within the synthesizer used to generate dot clock 0. See the appendix B for a
detailed description of the process used to derive the loop parameter values.
This bit always returns the value of 0 when read.
This bit selects a value that specifies the VCO loop divide, one of the loop parameters used
in controlling the frequency of the output of the synthesizer used to generate dot clock 0.
0: Selects a VCO loop divide value of 4.
1: Selects a VCO loop divide value of 1.
A series of calculations are used to derive this value and the values for the other loop
parameters given a desired output frequency and a series of constraints placed on different
components within the synthesizer used to generate dot clock 0. See appendix B for a
detailed description of the process used to derive the loop parameter values.
These bits always return the value 0 when read.
6
Post Divisor Select
5
Subject to Change Without Notice
6 5 4
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Bits
Extension Registers
4
Post Divisor
Reserved
Reserved
Reserved
16
32
1
2
4
8
3
VCO Loop
Divisor
2
Revision 1.3 8/31/98
1
Reserved
0