B69000 Asiliant Technologies, B69000 Datasheet - Page 220

• Manufacturer Part Number: B69000
• Manufacturer: Asiliant Technologies

Specifications of B69000

• Lead Free Status / Rohs Status: Supplier Unconfirmed

FR05
read/write at I/O address 3D1h with index at I/O address 3D0h set to 05h
7
6
5
4
3
2-0
&+,36
CRT Mode
(0)
7
CRT Mode Control
0: Flat panel data and control signals are tri-stated with weak internal pull-down (default).
1: Flat panel data and control signals are driven inactive.
This bit is effective only in CRT mode (flat panel is not active).
Reserved
This bit should always be written to with a value of zero.
Standby and Panel Off Control
0: Flat panel data and control signals are driven inactive (default).
1: Flat panel data and control signals are tri-stated with a weak internal pull-down.
This bit is effective in Flat Panel Mode during Standby and Panel Off modes. This bit does not affect
CRT control signals which will be driven low.
Host Standby Mode
0: Normal Mode (default)
1: Standby Mode
This bit disables the CPU interface, but allows the display to remain active. All CPU interface
activity is ignored except RESET#. This bit can be cleared (re-enabling the CPU interface) by
RESET# or a low-to-high transition on STNDBY#
Panel Off Mode
0 : Normal mode (default)
1: Panel Off mode
When this bit is set, the chip enters Panel Off mode. In this mode, CRT/FP screen refresh is inactive
but CPU interface and display memory refresh are still active. Display memory and I/O registers
can still be accessed.
FP Normal Refresh Count (default = 001)
These bits specify the number of memory refresh cycles per scanline. These bits should have a
minimum value of 001.
69000 Databook
Power Down Control 1 Register
Reserved
(0)
6
Panel Off
(0)
5
Subject to Change Without Notice
Host Stby
Flat Panel Registers
(0)
4
Off Mode
(0)
3
2
FP Norm Refresh
(001)
Revision 1.3 8/31/98
1
0
15-5