B69000 Asiliant Technologies, B69000 Datasheet - Page 348

• Manufacturer Part Number: B69000
• Manufacturer: Asiliant Technologies

Specifications of B69000

• Lead Free Status / Rohs Status: Supplier Unconfirmed

BitBLT Operation
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engine requires only four pieces of information: the starting address of the first sub-block, the length of a
sub-block, the offset (in bytes) of the starting address of each subsequent sub-block, and the quantity of
sub-blocks.
Figure E-7: On-Screen 6x4 Array of Pixels in the Frame Buffer
Source Data
The source data may either exist in the frame buffer where the BitBLT engine may read it directly, or it may
be provided to the BitBLT engine by the host CPU. The block of source graphics data may be either
contiguous or discontiguous, and may be either in color (with a color depth that matches that to which the
BitBLT engine has been set) or monochrome.
Bit 10 of the BitBLT Control Register (BR04) specifies whether the source data exists in the frame buffer or
is provided by the CPU. Having the source data in the frame buffer will result in increased performance
since the BitBLT engine will be able to access it directly without involving the host CPU.
If the source data resides within the frame buffer, then the Source Address Register (BR06) is used to
specify the address of the source data as an offset from the beginning of the frame buffer at which the block
of source data begins. However, if the host CPU provides the source data, then this register takes on a
different function and the three least-significant bits of the Source Address Register (BR06) can be used to
specify a number of bytes that must be skipped in the first quadword received from the host CPU to reach
the first byte of valid source data.
In cases where the host CPU provides the source data, it does so by writing the source data to the BitBLT
data port, a 64KB memory space on the host bus. There is no actual memory allocated to this memory
space, so any data that is written to this location cannot be read back. This memory space is simply a range
of memory addresses that the BitBLT engine’s address decoder watches for the occurrence of any memory
writes. The BitBLT engine loads all data written to any memory address within this memory space in the
order in which it is written, regardless of the specific memory address to which it is written and uses that
data as the source data in the current BitBLT operation. The block of bytes sent by the host CPU to this
data port must be quadword-aligned, although the source data contained within the block of bytes does not
need to be aligned. As mentioned earlier, the least significant three bits of the Source Address Register
(BR06) are used to specify the number of bytes that must be skipped in the first quadword to reach the first
byte of valid source data.
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69000 Databook
Subject to Change Without Notice
Revision 1.3 8/31/98